Resolver excitation circuit

Claim 2

A resolver excitation circuit for correcting phase difference between a digital timing reference signal and a sinusoidal excitation signal, the resolver excitation circuit comprising: memory means for storing words of waveform data as a sequence of digitized waveform values for the sinusoidal excitation signal; first latch means for sequentially receiving words of waveform data from the memory means, the first latch means storing one word of waveform data at one time; means for generating a plurality of addresses to the memory means to cause output of a plurality of the words of waveform data to the first latch means over a portion of one cycle of the sinusoidal excitation signal; digital-to-analog converter means responsive to waveform data received from the first latch means for converting the waveform data to an analog signal that controls sinusoidal excitation signal; means for generating a digital timing reference signal; phase difference detection means for detecting a phase difference between the sinusoidal excitation signals and the digital timing reference signal; and phase correction means for controlling the time of output of each word of waveform data from the first latch means to the digital-to-analog converter means in response to the detection of a phase difference by the phase detection means to correct the phase of the sinusoidal excitation signal.

Claim 3

The resolver excitation circuit of claim 1, wherein the phase difference detection means includes: means for generating timing signal synchronized to the digital timing reference signal; counter means responsive to the timing signals to accumulate an elapsed time count; a second latch means for receiving the elapsed time count; means responsive to the sinusoidal excitation signal crossing a zero threshold for generating a clock signal to the second latch means to enable the second latch means to receive and hold the elapsed time count; and means for receiving the elapsed time count from the output of the second latch means including means for comparing the elapsed time count with a predetermined count for the crossing of the zero threshold to generate a phase difference signal.

Claim 4

The resolver excitation circuit of claim 1 wherein the phase correcting means includes: variable voltage supply means responsive to the detection of a phase difference by the phase detection means to generate a phase correction voltage signal; means for generating a ramp signal synchronized to the digital timing reference signal; and means for comparing the phase correction voltage signal to the ramp signal including means for generating a clock signal to the first latch means to control the time of output of a word of waveform data from the first latch means to the digital-to-analog converter means.

Claim 5

The resolver excitation circuit of claim 1 further including: voltage reference means for generating a constant voltage; amplitude detection means for detecting an amplitude difference between the sinusoidal excitation signal and the voltage reference; scaling mean s for scaling the analog signal; amplitude correction means for controlling the scaling means in response to detection of an amplitude difference by the amplitude detection means to correct the amplitude of the analog signal that controls the sinusoidal excitation signal.

Claim 6

A resolver excitation circuit for correcting phase differences between two sinusoidal excitation signals that differ in phase by approximately ninety degrees, the resolver excitation circuit comprising: memory means for storing waveform words as a sequence of digitized waveform values for the sinusoidal excitation signals; demultiplexer means for sequentially receiving and storing a word pair from the memory, each word of the pair associated with digitized waveform value for one of the sinusoidal excitation signals at a corresponding phase; first latch means for independently receiving each word of one word pair from the demultiplexer means, means for generating a plurality of addresses to the memory to cause output of a plurality of the word pairs of waveform data to the demultiplexer means over a portion of corresponding cycles of each the sinusoidal excitation signals; digital-to-analog converter means independently responsive to each word of the word pair received from the first latch means for converting the word pairs into two analog signals that control the sinusoidal excitation signals associated with each word; means for generating a digital timing reference signal; phase difference detection means for detecting a phase difference between each of the sinusoidal excitation signals and the digital timing reference signal; and phase correction means for independently controlling the time of output of each word of the word pair from the first latch means to the digital-to-analog converter means in response to the detection of a phase difference by the phase detection means to correct the phase of the sinusoidal excitation signals.

Claim 7

A resolver excitation circuit for correcting phase differences between two sinusoidal excitation signals that differ in phase by approximately ninety degrees, the resolver excitation circuit comprising: memory means for storing waveform words as a sequence of digitized waveform values for the sinusoidal excitation signals; demultiplexer means for sequentially receiving and storing a word pair from the memory, each word of the pair associated with digitized waveform value for one of the sinusoidal excitation signals at a corresponding phase; first latch means for independently receiving each word of one word pair from the demultiplexer means, means for generating a plurality of addresses to the memory to cause output of a plurality of the word pairs of waveform data to the demultiplexer means over a portion of corresponding cycles of each the sinusoidal excitation signals; digital-to-analog converter means independently responsive to each word of the word pair received from the first latch means for converting the word pairs into two analog signals that control the sinusoidal excitation signals associated with each word; means for generating a digital timing reference signal; phase difference detection means for detecting a phase difference between each of the sinusoidal excitation signals and the digital timing reference signal; and phase correction means for independently controlling the time of output of each word of the word pair from the first latch means to the digital-to-analog converter means in response to the detection of a phase difference by the phase detection means to correct the phase of the sinusoidal excitation signals.