US4970637A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital anti-aliasing filter
Assignee: Toshiba Corp
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Filing: 1988-06-20
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Granted: 1990-11-13
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Expires: 2008-06-20
Abstract
Abstract An original analog signal is supplied to A/D converter 2 through analog LPF 1. LPF 1 has a cutoff frequency of fa/2 (fa is the frequency of a clock pulse supplied to A/D converter 2). LPF 1 limits a frequency band determined by filter characteristics. An output from A/D converter 2 is supplied to sample circuit 4 through maximum filter 3. An output from sample circuit 4 is supplied to a circuit of the next stage as final output Dout. Maximum filter 3 can arbitrarily set the number of sampling interval data (filter width). Maximum filter 3 is a nonlinear filter for outputting a maximum value of input data within a set filter width as a representative value of the width. The clock pulse of frequency fa is also supplied to maximum filter 3 so that input/output operation of data is synchronized with the clock pulse. The filter width of maximum filter 3 is determined in accordance with fa/fb (fb is the frequency of a clock pulse supplied to sample circuit 4 , and fa≧fb).
Inventors
- 👤 Takeshi Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:34
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/0248; H03H17/0261; H03H17/0263; G; G01; G01S; G01S7/00; G01S7/52; G01S7/52017; G01S7/52023; G01S7/52025; G01S7/52026; G01S7/52028
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
94 words
A sampling circuit comprising: a nonlinear digital filter means for receiving digital data, for storing a number W of past values of the received digital data, and for outputting the largest value of said W stored past values of said digital data, the storing and outputting occurring synchronously with a first clock signal having a first frequency; and a sampling means for sampling the outputted largest values from said nonlinear digital filter synchronously with a second clock signal having a second frequency, said first frequency being at least as high as said second frequency.
Claim 2
Dependent Claim
94 words
A sampling circuit comprising: a nonlinear digital filter means for receiving digital data, for storing a number W of past values of the received digital data, and for outputting the largest value of said W stored past values of said digital data, the storing and outputting occurring synchronously with a first clock signal having a first frequency; and a sampling means for sampling the outputted largest values from said nonlinear digital filter synchronously with a second clock signal having a second frequency, said first frequency being at least as high as said second frequency.
Claim 3
Dependent Claim
46 words
The sampling circuit according to claim 1, further comprising: an A/D converter means for converting an input analog signal into digital data and for outputting said digital data to said nonlinear digital filter means, the converting and the outputting occurring synchronously with said first clock signal.
Claim 4
Dependent Claim
29 words
The sampling circuit according to claim 1 wherein said nonlinear digital filter has a cutoff frequency and wherein said number W can be changed to change said cutoff frequency.
Claim 5
Dependent Claim
94 words
A sampling circuit comprising: a nonlinear digital filter means for receiving digital data, for storing a number W of past values of the received digital data, and for outputting the smallest value of said W stored past values of said digital data, the storing and outputting occurring synchronously with a first clock signal having a first frequency; and a sampling means for sampling the outputted smallest values from said nonlinear digital filter synchronously with a second clock signal having a second frequency, said first frequency being at least as high as said second frequency.
Claim 6
Dependent Claim
94 words
A sampling circuit comprising: a nonlinear digital filter means for receiving digital data, for storing a number W of past values of the received digital data, and for outputting the smallest value of said W stored past values of said digital data, the storing and outputting occurring synchronously with a first clock signal having a first frequency; and a sampling means for sampling the outputted smallest values from said nonlinear digital filter synchronously with a second clock signal having a second frequency, said first frequency being at least as high as said second frequency.
Claim 7
Dependent Claim
46 words
The sampling circuit according to claim 4, further comprising: an A/D converter means for converting an input analog signal into digital data and for outputting said digital data to said nonlinear digital filter means, the converting and the outputting occurring synchronously with said first clock signal.
Claim 8
Dependent Claim
29 words
The sampling circuit according to claim 4 wherein said nonlinear digital filter has a cutoff frequency and wherein said number W can be changed to change said cutoff frequency.
Claim 9
Dependent Claim
94 words
A sampling circuit comprising: a nonlinear digital filter means for receiving digital data, for storing a number W of past values of the received digital data, and for outputting the average value of said W stored past values of said digital data, the storing and outputting occurring synchronously with a first clock signal having a first frequency; and a sampling means for sampling the outputted average values from said nonlinear digital filter synchronously with a second clock signal having a second frequency, said first frequency being at least as high as said second frequency.
Claim 10
Dependent Claim
94 words
A sampling circuit comprising: a nonlinear digital filter means for receiving digital data, for storing a number W of past values of the received digital data, and for outputting the average value of said W stored past values of said digital data, the storing and outputting occurring synchronously with a first clock signal having a first frequency; and a sampling means for sampling the outputted average values from said nonlinear digital filter synchronously with a second clock signal having a second frequency, said first frequency being at least as high as said second frequency.
Claim 11
Dependent Claim
46 words
The sampling circuit according to claim 7, further comprising: an A/D converter means for converting an input analog signal into digital data and for outputting said digital data to said nonlinear digital filter means, the converting and the outputting occurring synchronously with said first clock signal.
Claim 12
Dependent Claim
30 words
The sampling circuit according to claim 7 in wherein said nonlinear digital filter has a cutoff frequency and wherein said number W can be changed to change said cutoff frequency.
Claim 13
Dependent Claim
221 words
An ultrasonic tomographic imaging apparatus for displaying tomographic image data on a CRT display, comprising: an A/D converter means for converting a reflected ultrasonic echo signal representing a tomographic image into digital data and for outputting said digital data, the converting and outputting occurring synchronously with a first clock signal having a first frequency; a nonlinear low pass digital filter means for receiving said digital data from said A/D converter means, for storing a number W of past values of the received digital data, and for outputting low pass filtered digital data based on a manipulation of said W past values, the storing and outputting occurring synchronously with a first clock signal having a first frequency; a buffer memory means for receiving, storing, and outputting the output data from said nonlinear low pass digital filter means, the receiving occurring synchronously with said first clock signal having said first frequency, the outputting occurring synchronously with the a second clock signal having a second frequency, said first frequency being at least as high as said second frequency; and a frame memory means for receiving the output data from said buffer memory means synchronously with said second clock signal, and for outputting said output data synchronously with a third clock signal having a third frequency corresponding to the display speed of the CRT display.
Claim 14
Dependent Claim
221 words
An ultrasonic tomographic imaging apparatus for displaying tomographic image data on a CRT display, comprising: an A/D converter means for converting a reflected ultrasonic echo signal representing a tomographic image into digital data and for outputting said digital data, the converting and outputting occurring synchronously with a first clock signal having a first frequency; a nonlinear low pass digital filter means for receiving said digital data from said A/D converter means, for storing a number W of past values of the received digital data, and for outputting low pass filtered digital data based on a manipulation of said W past values, the storing and outputting occurring synchronously with a first clock signal having a first frequency; a buffer memory means for receiving, storing, and outputting the output data from said nonlinear low pass digital filter means, the receiving occurring synchronously with said first clock signal having said first frequency, the outputting occurring synchronously with the a second clock signal having a second frequency, said first frequency being at least as high as said second frequency; and a frame memory means for receiving the output data from said buffer memory means synchronously with said second clock signal, and for outputting said output data synchronously with a third clock signal having a third frequency corresponding to the display speed of the CRT display.
Claim 15
Dependent Claim
36 words
The tomographic imaging apparatus of claim 10 wherein said manipulation of said W past values constitutes a maximum filter in which said outputted low pass filtered data is the largest value of said W past values.
Claim 16
Dependent Claim
36 words
The tomographic imaging apparatus of claim 10 wherein said manipulation of said W past values constitutes a minimum filter in which said outputted low pass filtered data is the smallest value of said W past values.
Claim 17
Dependent Claim
36 words
The tomographic imaging apparatus of claim 10 wherein said manipulation of said W past values constitutes a median filter in which said outputted low pass filtered data is the average value of said W past values.
Claim 18
Dependent Claim
68 words
The tomographic imaging apparatus of any one of claims 11 through 13 wherein said nonlinear low pass digital filter means has a cutoff frequency which decreases when the number W is increased for a constant frequency of said first clock signal, said cutoff frequency being controlled by changing said number W so that said cutoff frequency remains approximately equal to half the frequency of said second clock signal.
Claim 19
Dependent Claim
43 words
The tomographic imaging apparatus of claim 14 wherein the tomographic image data is displayed on said CRT at a variable magnification and wherein said frequency of said second clock signal is changed due to a change in displayed magnification of the tomographic image.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-12 | 1994-05-14 | 1994-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-12 | 1998-05-14 | 1998-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-12 | 2002-05-14 | 2002-11-13 | $7700.00 | Window Closed / Lapsed |