US4970582A
Expired / Lapsed
US
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Method and circuit for recovering a logic signal from a band limited signal channel
Assignee: Skotel Corp
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Filing: 1989-06-23
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Granted: 1990-11-13
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Expires: 2009-06-23
Abstract
Abstract A method and circuit for recovering from a video signal a digital Vertical Interval Time and Control Code (VITC) signal which has been distorted in the recording process. The video signal is passed through an appropriate high pass (differentiating) filter to remove all but the narrow spectrum associated with the rising and falling edges of the NRZ modulated VITC signal. Optionally, the signal may be low-pass filtered to improve noise immunity and remove any chroma or burst frequency components. The resulting output signal is a separate series of positive and negative pulses with an average DC value of zero. These pulses correspond to the rising and falling edges of the original VITC signal, are detected and used to reconstruct the original VITC signal. The positive pulses are delayed and then used to set a flip-flop while the negative pulses are used to reset the flip-flop. The output of the flip-flop will substantially correspond to the original VITC signal.
Inventors
- 👤 Stephen Scott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 05:18
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/93; G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/30; G11B27/3027; G11B27/3036; G11B27/3054
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
72 words
A method of recovering a bi-level logic signal which has been distorted which includes the steps of: a. filtering the signal to substantially remove frequency components not associated with the rising and falling edges of the bi-level logic signal to obtain two separate pulses corresponding respectively to the rising and falling edges of the logic signal; b. detecting the series of pulses; and c. reconstructing the bi-level logic signal from the pulses.
Claim 2
Independent Claim
72 words
A method of recovering a bi-level logic signal which has been distorted which includes the steps of: a. filtering the signal to substantially remove frequency components not associated with the rising and falling edges of the bi-level logic signal to obtain two separate pulses corresponding respectively to the rising and falling edges of the logic signal; b. detecting the series of pulses; and c. reconstructing the bi-level logic signal from the pulses.
Claim 3
Dependent Claim
23 words
The method of claim 1 wherein the bi-level logic signal is a vertical interval time and control code combined with a video signal.
Claim 4
Independent Claim
109 words
A method of recovering a bi-level logic signal comprising the steps of: a. filtering the signal to substantially remove frequency components not associated with the rising and falling edges of the bi-level logic signal, leaving a series of positive and negative pulses corresponding to the rising and falling edges of the logic signal; b. comparing the series of pulses to a continuously varying average signal level derived from the series of pulses to produce signals representative of leading and trailing edges of the original undistorted bi-level logic signal; c. detecting the leading and trailing edge signals and reconstructing the bi-level logic signal from the leading and trailing edge signals.
Claim 5
Independent Claim
109 words
A method of recovering a bi-level logic signal comprising the steps of: a. filtering the signal to substantially remove frequency components not associated with the rising and falling edges of the bi-level logic signal, leaving a series of positive and negative pulses corresponding to the rising and falling edges of the logic signal; b. comparing the series of pulses to a continuously varying average signal level derived from the series of pulses to produce signals representative of leading and trailing edges of the original undistorted bi-level logic signal; c. detecting the leading and trailing edge signals and reconstructing the bi-level logic signal from the leading and trailing edge signals.
Claim 6
Dependent Claim
23 words
The method of claim 3 wherein the bi-level logic signal is a vertical interval time and control code included in a video signal.
Claim 7
Dependent Claim
163 words
A circuit for recovering a bi-level logic signal comprising: a. input means for receiving an input bi-level logic signal; b. buffer means connected to said input means for buffering the input signal to produce a buffered signal; c. filter means connected to receive said buffered signal, said filter means operating to filter the buffered signal to produce filtered output signals having components corresponding to the rising and falling edges of the bi-level logic signal; d. level detecting means connected to receive said filtered output signals and responsive to the filtered signal components corresponding to the rising and falling edges of the bi-level logic signal; said detecting means producing level detected signals corresponding to the rising and falling edges of the bi-level logic signal; and e. reconstructing means for producing a signal which is a substantial reproduction of the original bi-level logic signal from the level detected signals produced by the detecting means, said reconstructing means being connected to receive said level detected signals.
Claim 8
Dependent Claim
163 words
A circuit for recovering a bi-level logic signal comprising: a. input means for receiving an input bi-level logic signal; b. buffer means connected to said input means for buffering the input signal to produce a buffered signal; c. filter means connected to receive said buffered signal, said filter means operating to filter the buffered signal to produce filtered output signals having components corresponding to the rising and falling edges of the bi-level logic signal; d. level detecting means connected to receive said filtered output signals and responsive to the filtered signal components corresponding to the rising and falling edges of the bi-level logic signal; said detecting means producing level detected signals corresponding to the rising and falling edges of the bi-level logic signal; and e. reconstructing means for producing a signal which is a substantial reproduction of the original bi-level logic signal from the level detected signals produced by the detecting means, said reconstructing means being connected to receive said level detected signals.
Claim 9
Dependent Claim
36 words
The circuit of claim 5 including means for amplifying the filtered output signals connected to said filter means, and means for blocking direct current components of the amplified filtered output signals connected to said amplifying means.
Claim 10
Dependent Claim
44 words
The circuit of claim 5 wherein said filter means provides filtered output signals consisting substantially of positive and negative pulses, and the detecting means comprises two comparators, one of which is responsive to positive pulses and the remaining one being responsive to negative pulses.
Claim 11
Dependent Claim
46 words
The circuit of claim 7 which includes reference signal generating means connected to receive said filtered output signals, said reference signal generating means providing a varying signal representing the average level of the filtered output signals as a reference input to each of the said comparators.
Claim 12
Dependent Claim
30 words
The circuit of claim 7 wherein the reconstruction means is an SR flip-flop having set and reset inputs, each connected to receive an output signal from one of the comparators.
Claim 13
Dependent Claim
37 words
The circuit of claim 9 wherein the input bi-level logic signal is a vertical time and control code included in a video signal, said vertical time and control code having signals components with leading and trailing edges.
Claim 14
Dependent Claim
35 words
The circuit of claim 10 wherein the level detected signals include positive pulses corresponding to the leading edges and negative pulses corresponding to the trailing edges of the vertical time and control code signal components.
Claim 15
Dependent Claim
40 words
The circuit of claim 11 wherein the positive pulses of the level 11 detected signals are provided to the set input of the SR flip-flop and the negative pulses of the level detected signals are provided to the reset input.
Claim 16
Dependent Claim
29 words
The circuit of claim 12 wherein synchronization means are connected between said level detecting means and said SR flip-flop to delay the positive pulses of the level detected signals.
References Cited (Backward Citations)
US3831193A
Cited
US3987484A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-12 | 1994-05-14 | 1994-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-12 | 1998-05-14 | 1998-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-12 | 2002-05-14 | 2002-11-13 | $7700.00 | Window Closed / Lapsed |