Abstract Formation of an interconnect structure having a self-planarized dielectric layer between successive layers of metallization is accomplished by conformally depositing a dielectric layer over the entire structure (including underlying regions and contact base metallization) to which the interconnect pattern is to be plated. Atop the dielectric layer a sacrificial layer is conformally deposited. Thereafter apertures are etched through both the sacrificial and dielectric layers in accordance with a prescribed interconnect plating pattern that has been photolithographically mapped onto the laminate structure. The aspect ratios of the apertures through the laminate are such that metal to be subsequently deposited therethrough is confined to the exposed surface area of the underlying topography but not on the sidewalls of the apertures through the dielectric layer. The sacrificial layers (and overlying metal plate) are then removed leaving only the patterned conformed dielectric layer and the deposited metal. The main body portion of the interconnect structure is now plated onto the deposited metal pattern to a thickness in the apertures of the dielectric which is slightly below the top surface of the dielectric layer. Thereafter, a second, thin dielectric layer is non-selectively conformally deposited over the entire structure. Contact vias for a second layer of metal to be formed over the top surface of the second dielectric layer are selectively etched through this second dielectric layer to expose surface portions of the underlying plated metal.
Inventors
👤 Bruce E. Roberts
👤 Jimmy C. Black
👤 George E. Mraz
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-04 00:28
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
171 words
An interconnect structure for a semiconductor device comprising: a first dielectric layer of substantially uniform thickness conformally disposed over the surface of a semiconductor substrate and having apertures therein extending to prescribed surface portions of said substrate; respective conductive layers formed on said prescribed surface portions of said substrate but not effectively on sidewalls of said apertures; respective layers of conductive material formed within said apertures and extending from the top surfaces of said conductive layers to a thickness less than the thickness of said first dielectric layer; a second dielectric layer of substantially uniform thickness conformally disposed over the surface of said first dielectric layer and the respective layers of conductive material disposed in the apertures therein, said second dielectric layer having apertures therein exposing portions of the top surfaces of said layers of conductive material; and a conductive interconnection layer disposed on the top surface of said second dielectric layer and extending through apertures therein to said exposed portions of the top surface of said layers of conductive material.
Claim 2
Dependent Claim
171 words
An interconnect structure for a semiconductor device comprising: a first dielectric layer of substantially uniform thickness conformally disposed over the surface of a semiconductor substrate and having apertures therein extending to prescribed surface portions of said substrate; respective conductive layers formed on said prescribed surface portions of said substrate but not effectively on sidewalls of said apertures; respective layers of conductive material formed within said apertures and extending from the top surfaces of said conductive layers to a thickness less than the thickness of said first dielectric layer; a second dielectric layer of substantially uniform thickness conformally disposed over the surface of said first dielectric layer and the respective layers of conductive material disposed in the apertures therein, said second dielectric layer having apertures therein exposing portions of the top surfaces of said layers of conductive material; and a conductive interconnection layer disposed on the top surface of said second dielectric layer and extending through apertures therein to said exposed portions of the top surface of said layers of conductive material.
Claim 3
Dependent Claim
18 words
An interconnect structure according to claim 1, wherein said respective layers of conductive material comprise plated metal layers.