Semiconductor memory device having serial addressing and operating method thereof

Claim 2

A semiconductor memory device comprising memory means for storing data, having a plurality of address terminals for receiving in parallel address information for reading said data, and at least one data terminal for outputting said data; means for temporarily disabling said memory means, said at least one data terminal serially receiving the address information from an external source only during a period when said memory means is in the disabled state; and shift register means having a serial input terminal connected to said one of said at least one data terminal for converting said address information received in series to parallel address information to supply the same to the plurality of address terminals of said memory means.

Claim 3

A semiconductor memory device according to claim 1, wherein said shift register means comprises a clock terminal for externally receiving a shift clock signal.

Claim 4

A semiconductor memory device according to claim 2, wherein said address information serially received is a binary digit string in accordance with an exhaustive random sequence.

Claim 5

A semiconductor memory device according to claim 3, wherein said shift register means is a bidirectional shift register.

Claim 6

A semiconductor memory device comprising: a plurality of memory means for storing data, each having a plurality of address terminals receiving in parallel address information for reading said data, and at least one data terminal for outputting said data; at least one external data terminal connected together to the data terminals of said plurality of memory means; means for temporarily disabling each of said plurality of memory means, said at least one external data terminal receiving in series the address information from an external source only during a period when all of said plurality of memory means are in the disabled state to supply the same commonly to the data terminals of said memory means and; a plurality of shift register means provided in one to one correspondence with said memory means, each of said shift register means having a serial input terminal connected to the data terminal which is connected to said at least one external data terminal, said shift register means converting said serially received address information to parallel address information to supply the same to the plurality of address terminals of the corresponding memory means.

Claim 7

A semiconductor memory device comprising: a plurality of memory means for storing data, each having a plurality of address terminals receiving in parallel address information for reading said data, and at least one data terminal for outputting said data; at least one external data terminal connected together to the data terminals of said plurality of memory means; means for temporarily disabling each of said plurality of memory means, said at least one external data terminal receiving in series the address information from an external source only during a period when all of said plurality of memory means are in the disabled state to supply the same commonly to the data terminals of said memory means and; a plurality of shift register means provided in one to one correspondence with said memory means, each of said shift register means having a serial input terminal connected to the data terminal which is connected to said at least one external data terminal, said shift register means converting said serially received address information to parallel address information to supply the same to the plurality of address terminals of the corresponding memory means.

Claim 8

A semiconductor memory device according to claim 5, wherein said plurality of shift register means comprise clock terminals for externally receiving shift clock signals in common.

Claim 9

A semiconductor memory device according to claim 5, wherein said address information serially received is a binary digit string in accordance with an exhaustive random sequence.

Claim 10

A semiconductive memory device according to claim 7, wherein each of said plurality of shift register means is a bidirectional shift register.

Claim 11

A semiconductor memory device comprising: memory means for storing data, having a plurality of address terminals for receiving in parallel address information for reading/writing said data, and at least one data terminal for inputting and outputting said data; a first shift register means externally receiving in series address information for data reading to convert said series address information to first parallel address information; a second shift register means externally receiving in series address information for data writing to convert said series address information to second parallel address information, said serial address information being a binary digit string in accordance with an n valued exhaustive random sequence wherein an arbitrary binary value represented by continuous n bits is different from any other binary value represented by an arbitrary continuous n bits in the binary digit string; and selector means alternatively selecting either the address information supplied from said first shift register means or the address information from said second shift register means to supply the same to the address terminals of said memory means.

Claim 12

A semiconductor memory device comprising: memory means for storing data, having a plurality of address terminals for receiving in parallel address information for reading/writing said data, and at least one data terminal for inputting and outputting said data; a first shift register means externally receiving in series address information for data reading to convert said series address information to first parallel address information; a second shift register means externally receiving in series address information for data writing to convert said series address information to second parallel address information, said serial address information being a binary digit string in accordance with an n valued exhaustive random sequence wherein an arbitrary binary value represented by continuous n bits is different from any other binary value represented by an arbitrary continuous n bits in the binary digit string; and selector means alternatively selecting either the address information supplied from said first shift register means or the address information from said second shift register means to supply the same to the address terminals of said memory means.

Claim 13

A semiconductor memory device according to claim 9, wherein said first and second shift register means include separate clock terminals for receiving external shift clock signals.

Claim 14

A semiconductor memory device according to claim 10, wherein each of said first and second shift register means is a bidirectional shift register.

Claim 15

A semiconductor memory device according to claim 10, further comprising an external terminal for receiving an external signal controlling switching operation of said selector means.

Claim 16

A semiconductor memory device according to claim 10, further comprising means for temporarily disabling said memory means.

Claim 17

A semiconductor memory device according to claim 13, wherein said memory means has a plurality of data terminals, one of said plurality of data terminals receives in series said address information for data reading from an external source and another one of said plurality of data terminals receives in series said address information for data writing from an external source only during a period when said memory means is at the disabled state; said first shift register means includes a serial input terminal connected to said one of said plurality of data terminals; and said second shift register means includes a serial input terminal connected to said another one of said plurality of data terminals.

Claim 18

A semiconductor memory device according to claim 13, wherein said selector means receives a signal for controlling switching operation of said selector means from said means for disabling said memory means.

Claim 19

A semiconductor memory device according to claim 9, further comprising an external clock terminal commonly connected to the clock terminals of said first and second shift register means for receiving external shift clock signals.

Claim 20

A semiconductor memory device comprising: a plurality of memory means for storing data, each having a plurality of address terminals receiving in parallel address information for reading said data, and at least one data terminal for outputting said data; a plurality of comparing means provided in one to one correspondence with said memory means; a plurality of identification code generating means provided in one to one correspondence with said memory means for generating a specified identification code identifying each of the memory means and supplying the same to one input of said comparing means; and a plurality of shift register means provided in one to one correspondence with said memory means for receiving in common external address information in series, each of said shift register means converting said received serial address information to parallel address information to supply address information for data reading to the address terminals of the corresponding memory means and to supply address information identifying said corresponding memory means to another input of said comparing means; wherein each of said comparing means compares the identification code generated from the corresponding identification code generating means with the address information outputted from said corresponding shift register and generates a signal prohibiting the operation of the corresponding memory means to the memory means when a predetermined condition is satisfied.

Claim 21

A semiconductor memory device comprising: a plurality of memory means for storing data, each having a plurality of address terminals receiving in parallel address information for reading said data, and at least one data terminal for outputting said data; a plurality of comparing means provided in one to one correspondence with said memory means; a plurality of identification code generating means provided in one to one correspondence with said memory means for generating a specified identification code identifying each of the memory means and supplying the same to one input of said comparing means; and a plurality of shift register means provided in one to one correspondence with said memory means for receiving in common external address information in series, each of said shift register means converting said received serial address information to parallel address information to supply address information for data reading to the address terminals of the corresponding memory means and to supply address information identifying said corresponding memory means to another input of said comparing means; wherein each of said comparing means compares the identification code generated from the corresponding identification code generating means with the address information outputted from said corresponding shift register and generates a signal prohibiting the operation of the corresponding memory means to the memory means when a predetermined condition is satisfied.

Claim 22

A semiconductor memory device according to claim 17, wherein each of said shift register means supplies in parallel address information, whose bit number is equal to a sum of a bit number of said address information for data reading and a bit number of said address information for identifying the memory means.

Claim 23

A semiconductor memory device according to claim 18, wherein said external address information is a binary digit string in accordance with an exhaustive random sequence.

Claim 24

A semiconductor memory device according to claim 19, wherein each of said shift register means is a bidirectional shift register.

Claim 25

An integrated circuit card comprising: external terminals, an integrated circuit, a memory device having a plurality of address nodes and at least one data terminal, a shift register having a clock terminal, a serial input terminal and parallel data output nodes corresponding to stages of said shift register, said memory device and said shift register being formed on said integrated circuit, said parallel data output nodes of said shift register being interconnected on said integrated circuit with said address nodes of said memory device, and said serial input terminal of said shift register and said at least one data terminal of said memory device being connected to the corresponding external terminals.

Claim 26

An integrated circuit card comprising: external terminals, an integrated circuit, a memory device having a plurality of address nodes and at least one data terminal, a shift register having a clock terminal, a serial input terminal and parallel data output nodes corresponding to stages of said shift register, said memory device and said shift register being formed on said integrated circuit, said parallel data output nodes of said shift register being interconnected on said integrated circuit with said address nodes of said memory device, and said serial input terminal of said shift register and said at least one data terminal of said memory device being connected to the corresponding external terminals.

Claim 27

An integrated circuit card according to claim 21, wherein said external terminals are connected to external circuitry, said external circuitry including means for supplying to said serial input terminal of said shift register serial addressing information for addressing said memory device.

Claim 28

For a semiconductor memory device having a plurality of address terminals for receiving from parallel address lines parallel address information for reading data and a plurality of data terminals for outputting said data on parallel data lines, an operating method, comprising the steps of, temporarily disabling said memory device, applying to only one of said data lines serial address information corresponding to a memory location in said memory device, receiving said serial address information on said one data line, converting said serial address information to parallel address information, enabling said memory device, and applying said parallel address information to said address terminals of said memory device.

Claim 29

For a semiconductor memory device having a plurality of address terminals for receiving from parallel address lines parallel address information for reading data and a plurality of data terminals for outputting said data on parallel data lines, an operating method, comprising the steps of, temporarily disabling said memory device, applying to only one of said data lines serial address information corresponding to a memory location in said memory device, receiving said serial address information on said one data line, converting said serial address information to parallel address information, enabling said memory device, and applying said parallel address information to said address terminals of said memory device.

Claim 30

For a semiconductor memory device having a plurality of address terminals for receiving in parallel address information for reading data and a plurality of data terminals for outputting said data, an addressing method, comprising the steps of, generating first serial exhaustive random sequence (ERS) data, shifting said first serial ERS data to provide second serial ERS data, converting said first and second serial ERS data to first and second parallel ERS data, and addressing said memory device alternately with said first and second parallel ERS data.

Claim 31

For a semiconductor memory device having a plurality of address terminals for receiving in parallel address information for reading data and a plurality of data terminals for outputting said data, an addressing method, comprising the steps of, generating first serial exhaustive random sequence (ERS) data, shifting said first serial ERS data to provide second serial ERS data, converting said first and second serial ERS data to first and second parallel ERS data, and addressing said memory device alternately with said first and second parallel ERS data.

Claim 32

A method according to claim 24, wherein shifting of said first and second serial ERS data is controlled in common.

Claim 33

A method according to claim 24, wherein alternate addressing of said memory device with said first and second parallel ERS data is controlled in synchronization with disabling of said memory device.

Claim 34

A method according to claim 24, wherein shifting of each of said first and second serial ERS data is made in a bidirectional manner.