US4969033A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for removing crosstalk components in a carrier chrominance signal
Assignee: Victor Company of Japan Ltd
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Filing: 1990-04-05
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Granted: 1990-11-06
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Expires: 2010-04-05
Abstract
Abstract In a circuit for removing crosstalk components in a carrier chrominance signal, there are provided a first delay circuit (20), an inverter (21), a first higher-voltage detecting circuit (18), a second delay circuit (22), a second higher-voltage detecting circuit (19), a third higher-voltage detecting circuit (25), a first lower-voltage detecting circuit (23), a second lower-voltage detecting circuit (24), a third lower-voltage detecting circuit (17), and an adder (26) thereby producing a crosstalk-removed carrier chrominance signal. Furthermore, the first delay circuit (20), the inverter (21), and an adder (28) form a comb filter for correcting a time delay due to said circuit for removing crosstalk components in a carrier chrominance signal.
Inventors
- 👤 Hiroshi Yamada
- 👤 Ryo Nakano
- 👤 Yasutoshi Matsuo
- 👤 Seiichi Mikami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 04:21
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/79; H04N9/7908; H04N9/7917; H04N9/64; H04N9/646; H04N9/80; H04N9/82; H04N9/83; H04N9/84
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
284 words
A circuit for removing crosstalk components in a carrier chrominance signal, comprising: (a) first delay circuit means responsive to said carrier chrominance signal; (b) inverter means responsive to an output signal from said first delay circuit means; (c) first higher-voltage detecting circuit means responsive to said carrier chrominance signal and an output signal from said inverter means for outputting a first highervoltage signal therebetween; (d) second delay circuit means responsive to said output signal from said first delay circuit means; (e) second higher-voltage detecting circuit means responsive to said output signal from said inverter means and an output signal from said second delay circuit means for outputting a second higher-voltage signal therebetween; (f) first lower-voltage detecting circuit means responsive to said first and second higher-voltage signals for outputting a first lower-voltage signal; (g) second lower-voltage detecting circuit means responsive to said carrier chrominance signal and said output signal from said inverter means for outputting a second lower-voltage signal therebetween; (h) third lower-voltage detecting circuit means responsive to said output signal from said inverter means and said output signal from said second delay circuit means for outputting a third lower-voltage signal therebetween; (i) third higher-voltage detecting circuit means responsive to said first and second lower-voltage signals for outputting a third higher-voltage signal; (j) first adder means responsive to said third highervoltage signal and said first lower-voltage signal thereby producing a crosstalk-removed carrier chrominance signal; and (k) a second adder means responsive to said carrier chrominance signal and to said output signal from said inverter means, said first delay circuit means, said inverter means and said second adder means comprising a comb filter for correcting a time delay due to said circuit for removing crosstalk components.
Claim 2
Dependent Claim
284 words
A circuit for removing crosstalk components in a carrier chrominance signal, comprising: (a) first delay circuit means responsive to said carrier chrominance signal; (b) inverter means responsive to an output signal from said first delay circuit means; (c) first higher-voltage detecting circuit means responsive to said carrier chrominance signal and an output signal from said inverter means for outputting a first highervoltage signal therebetween; (d) second delay circuit means responsive to said output signal from said first delay circuit means; (e) second higher-voltage detecting circuit means responsive to said output signal from said inverter means and an output signal from said second delay circuit means for outputting a second higher-voltage signal therebetween; (f) first lower-voltage detecting circuit means responsive to said first and second higher-voltage signals for outputting a first lower-voltage signal; (g) second lower-voltage detecting circuit means responsive to said carrier chrominance signal and said output signal from said inverter means for outputting a second lower-voltage signal therebetween; (h) third lower-voltage detecting circuit means responsive to said output signal from said inverter means and said output signal from said second delay circuit means for outputting a third lower-voltage signal therebetween; (i) third higher-voltage detecting circuit means responsive to said first and second lower-voltage signals for outputting a third higher-voltage signal; (j) first adder means responsive to said third highervoltage signal and said first lower-voltage signal thereby producing a crosstalk-removed carrier chrominance signal; and (k) a second adder means responsive to said carrier chrominance signal and to said output signal from said inverter means, said first delay circuit means, said inverter means and said second adder means comprising a comb filter for correcting a time delay due to said circuit for removing crosstalk components.
Claim 3
Dependent Claim
31 words
A circuit for removing crosstalk components in a carrier chrominance signal as claimed in claim 1, wherein said first and second delay circuit means are 1-H delay circuit in NTSC system.
Claim 4
Dependent Claim
31 words
A circuit for removing crosstalk components in a carrier chrominance signal as claimed in claim 1, wherein said first and second delay circuit means are 2-H delay circuit in PAL system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-05 | 1994-05-07 | 1994-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-05 | 1998-05-07 | 1998-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-05 | 2002-05-07 | 2002-11-06 | $7700.00 | Window Closed / Lapsed |