US4968950A
Expired / Lapsed
US
⏱️ 0.0 years remaining
PLL frequency synthesizer output control circuit
Assignee: Quarterhill Inc
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Filing: 1989-12-18
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Granted: 1990-11-06
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Expires: 2009-12-18
Abstract
Abstract A PLL frequency synthesizer IC chip having a sample frequency input terminal, data and address lines and a plurality of different output devices, and a mode control circuit for turning off any selected ones of the different output devices. The mode control circuit comprises a plurality of inputs connected to at least one of the data and address lines for determining different modes of operation, and a plurality of outputs connected to the plurality of different output devices for selecting ones of the plurality of different output devices to allow outputting therefrom and shutting off outputs from all of the remaining different output devices, based on the determined mode of operation.
Inventors
- 👤 David C. Babin
- 👤 Edward A. Kuligowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:49
CPC Classifications
H; H03; H03J; H03J5/00; H03J5/02; H03J5/0245; H03J5/0272; H03J5/0281; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
129 words
In a PLL frequency synthesizer IC chip having a sample frequency input terminal, data and address lines and a plurality of different output devices, a mode control circuit for turning off any selected ones of the plurality of different output devices, said mode control circuit comprising: first means having a plurality of inputs connected to at least one of the data and address lines, said first means determining different modes of operation of the PLL frequency synthesizer IC chip; and second means having a plurality of outputs connected to the plurality of different output devices for selecting ones of the plurality of different output devices to allow outputting therefrom and for shutting off outputs from all of the remaining different output devices, based on the determined mode of operation.
Claim 2
Dependent Claim
129 words
In a PLL frequency synthesizer IC chip having a sample frequency input terminal, data and address lines and a plurality of different output devices, a mode control circuit for turning off any selected ones of the plurality of different output devices, said mode control circuit comprising: first means having a plurality of inputs connected to at least one of the data and address lines, said first means determining different modes of operation of the PLL frequency synthesizer IC chip; and second means having a plurality of outputs connected to the plurality of different output devices for selecting ones of the plurality of different output devices to allow outputting therefrom and for shutting off outputs from all of the remaining different output devices, based on the determined mode of operation.
Claim 3
Dependent Claim
29 words
In a PLL frequency synthesizer IC chip, a mode control circuit according to claim 1, wherein said frequency synthesizer IC chip is a parallel input frequency synthesizer IC chip.
Claim 4
Dependent Claim
29 words
In a PLL frequency synthesizer IC chip, a mode control circuit according to claim 1, wherein said frequency synthesizer IC chip is a serial input frequency synthesizer IC chip.
Claim 5
Dependent Claim
124 words
In a PLL frequency synthesizer IC chip, a mode control circuit according to claim 1, wherein said IC chip is coupled to a voltage controlled oscillator through the sample frequency input terminal, and further comprises: reference frequency counting means for counting a reference frequency divided by a first number; sample frequency counting means coupled to the sample frequency input terminal for counting a sample frequency which is fed back from the voltage controlled oscillator and divided by a second number; and phase detecting means coupled to the reference frequency counting means and to the sample frequency counting means for comparing the count of the divided reference frequency and the count of the divided sample frequency, and providing an error signal based on the comparison.
References Cited (Backward Citations)
US4069462A
Cited
US4868513A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-05 | 1994-05-07 | 1994-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-05 | 1998-05-07 | 1998-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-05 | 2002-05-07 | 2002-11-06 | $7700.00 | Window Closed / Lapsed |