Semiconductor device having field effect transistors

Claim 2

A semiconductor device having an array of elemental cells, each of said elemental cells comprising: a semiconductor substrate having a main surface, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type positioned opposed to the first semiconductor region, and a trench formed in said semiconductor substrate, wherein a portion of side wall surface of said trench includes exposed surfaces of said first and second semiconductor regions; first and second impurity regions of the second conductivity type formed spaced apart from each other in said first semiconductor region, said first and second impurity regions defining in said first semiconductor region a first channel region including said exposed surface of said first semiconductor region; a first gate insulating layer formed in said trench on said exposed surface of the first semiconductor region of said first channel region; a first gate electrode formed in said trench on said first gate insulating layer; third and fourth impurity regions of the first conductivity type formed spaced apart from each other in said semiconductor region, said third and fourth impurity regions defining in said second semiconductor region a second channel region including said exposed surface of said second semiconductor region; a second gate insulating layer formed in said trench on said exposed surface of said second semiconductor region of said second channel region; and a second gate electrode formed in said trench on said second gate insulating layer.

Claim 3

A semiconductor device according to claim 1, wherein said first gate electrode and said second gate electrode comprise a common gate electrode in which the gate electrodes are formed integrally.

Claim 4

A semiconductor device according to claim 2, wherein said common gate electrode comprises an electrode portion positioned in said trench, and a contact portion formed extending from the electrode portion over upper surfaces of said first semiconductor region and said second semiconductor region, wherein an insulating layer is interposed between said contact portion and said upper surfaces of said first semiconductor region and said second semiconductor region, said contact portion having a surface electrically connected to a wiring layer.

Claim 5

A semiconductor device according to claim 1, wherein said trench formed in said semiconductor substrate is approximately rectangular; said first semiconductor region is approximately rectangular with one opened side, said first channel region formed at the center of and said first and second impurity regions formed on opposing end portions of the one opened side of said first semiconductor region; said second semiconductor region is approximately rectangular with one opened side, said second channel region formed at the center of and said third and fourth impurity regions formed on opposing end portions of the one opened side of said second semiconductor region; and said first gate electrode and said second gate electrode comprise a conductive layer formed in a region surrounded by said first semiconductor region and said second semiconductor region, said conductive layer being insulated therefrom and buried in said trench.

Claim 6

A semiconductor device according to claim 1, wherein first and second channel surfaces for respectively defining a magnitude of a carrier path in said first and second channel regions are formed in planes that are approximately perpendicular to the main surface of said semiconductor substrate.

Claim 7

A semiconductor device having an array of elemental cells, each of said elemental cells comprising: a semiconductor substrate having a main surface; a first semiconductor region of a first conductivity type and a first trench formed in said semiconductor substrate, wherein a portion of side wall surfaces of said first trench includes an exposed surface of said first semiconductor region; first and second impurity regions of a second conductivity type formed spaced apart from each other in said first semiconductor region, said first and second impurity regions defining a first channel region in said first semiconductor region including said exposed surface of said first semiconductor region; a first gate insulating layer formed in said first trench on said exposed surface of said first semiconductor region of said first channel region; a first gate electrode formed in said first trench on said first gate insulating layer; a second semiconductor region of the first conductivity type, a first side of said second semiconductor region being positioned approximately parallel to said first semiconductor region, a third semiconductor region of the second conductivity type positioned opposed to a second side of said second semiconductor region which is opposite from said first side, and a second trench formed in said semiconductor substrate, wherein a portion of side wall surface of said second trench includes exposed surfaces of said second and third semiconductor regions; third and fourth impurity regions of the second conductivity type formed spaced apart from each other in said second semiconductor region, said third and fourth impurity regions defining in said second semiconductor region a second channel region including said exposed surface of said second semiconductor region; a second gate insulating layer formed in said second trench on said exposed surface of the second semiconductor region of said second channel region; a second gate electrode formed in said second trench on said second gate insulating layer; fifth and sixth impurity regions of the first conductivity type formed spaced apart from each other in said third semiconductor region, said fifth and sixth impurity regions defining in said third semiconductor region a third channel region including said exposed surface of said third semiconductor region; a third gate insulating layer formed in said concave portion on said exposed surface of said third semiconductor region of said third channel region; and a third gate electrode formed in said second trench on said third gate insulating layer; wherein first, second and third channel surfaces for respectively defining a magnitude of a carrier path in said first, second and third channel regions are formed in planes that are approximately perpendicular to the main surface of said semiconductor substrate.

Claim 8

A semiconductor device having an array of elemental cells, each of said elemental cells comprising: a semiconductor substrate having a main surface; a first semiconductor region of a first conductivity type and a first trench formed in said semiconductor substrate, wherein a portion of side wall surfaces of said first trench includes an exposed surface of said first semiconductor region; first and second impurity regions of a second conductivity type formed spaced apart from each other in said first semiconductor region, said first and second impurity regions defining a first channel region in said first semiconductor region including said exposed surface of said first semiconductor region; a first gate insulating layer formed in said first trench on said exposed surface of said first semiconductor region of said first channel region; a first gate electrode formed in said first trench on said first gate insulating layer; a second semiconductor region of the first conductivity type, a first side of said second semiconductor region being positioned approximately parallel to said first semiconductor region, a third semiconductor region of the second conductivity type positioned opposed to a second side of said second semiconductor region which is opposite from said first side, and a second trench formed in said semiconductor substrate, wherein a portion of side wall surface of said second trench includes exposed surfaces of said second and third semiconductor regions; third and fourth impurity regions of the second conductivity type formed spaced apart from each other in said second semiconductor region, said third and fourth impurity regions defining in said second semiconductor region a second channel region including said exposed surface of said second semiconductor region; a second gate insulating layer formed in said second trench on said exposed surface of the second semiconductor region of said second channel region; a second gate electrode formed in said second trench on said second gate insulating layer; fifth and sixth impurity regions of the first conductivity type formed spaced apart from each other in said third semiconductor region, said fifth and sixth impurity regions defining in said third semiconductor region a third channel region including said exposed surface of said third semiconductor region; a third gate insulating layer formed in said concave portion on said exposed surface of said third semiconductor region of said third channel region; and a third gate electrode formed in said second trench on said third gate insulating layer; wherein first, second and third channel surfaces for respectively defining a magnitude of a carrier path in said first, second and third channel regions are formed in planes that are approximately perpendicular to the main surface of said semiconductor substrate.

Claim 9

A semiconductor device according to claim 6, wherein said second gate electrode and said third gate electrode comprise a common gate electrode in which the gate electrodes are formed integrally.

Claim 10

A semiconductor device according to claim 7, wherein said common gate electrode comprises an electrode portion positioned in said second trench, and a contact portion formed extending from the electrode portion over upper surfaces of said second semiconductor region and said third semiconductor region, wherein an insulating layer is interposed between said contact portion and said upper surfaces of said second semiconductor region and said third semiconductor region, said contact portion having a surface electrically connected to a wiring layer.

Claim 11

A semiconductor device according to claim 6, wherein said first and second trenches formed in said semiconductor substrate are approximately rectangular; said first semiconductor region is approximately rectangular with one opened side, said first channel region formed at the center of and said first and second impurity regions formed on opposing end portions of the one opened side of said first semiconductor region; said second semiconductor region is approximately rectangular with one opened side, said second channel region formed at the center of and said third and fourth impurity regions formed on opposing end portions of the one opened side of said second semiconductor region; said third semiconductor region is approximately rectangular with one opened side, said third channel region formed at the center of and said fifth and sixth impurity regions formed on opposing end portions of the one opened side of said third semiconductor region; and said second gate electrode and said third gate electrode comprise a conductive layer formed in a region surrounded by said second semiconductor region and said third semiconductor region, said layer being insulated therefrom and buried in said second trench.