US4965535A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple speed oscillator
Assignee: National Semiconductor Corp
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Filing: 1989-06-30
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Granted: 1990-10-23
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Expires: 2009-06-30
Abstract
Abstract A CMOS oscillator is disclosed using an inverter in which a pair of control terminals are employed to invoke various sized devices which control the flow of current. The inverter gain is determined by the size of the CMOS devices employed. A tuned circuit coupled to the inverter causes it to oscillate at the frequency of parallel resonance. The control terminals are coupled to the inverter invoke transistors that are sized as desired to establish the current flow and gain in the inverter. The current flow is controlled to optimize the gain of the inverter in terms of the frequency of oscillation. A Schmitt trigger can be employed to clean up the oscillator output for digital clock source applications.
Inventors
- 👤 Darren D. Neuman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:35
CPC Classifications
H; H03; H03B; H03B5/00; H03B5/30; H03B5/32; H03B5/36; H03B5/364
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
108 words
A multiple gain state amplifier circuit including input and output terminal between which a controlled gain is achieved in response to control input signals, said circuit comprising: a first two transistor inverter having the input electrodes of said two transistors connected to said input terminal and having the output electrodes of said two transistors coupled by first switch means to said output terminal, said first switch means being responsive to a first control input signal; and second switch means coupled between the output electrodes of said two transistors in said first inverter and said output terminal, said second swtich means being responsive to a second control input signal.
Claim 2
Dependent Claim
108 words
A multiple gain state amplifier circuit including input and output terminal between which a controlled gain is achieved in response to control input signals, said circuit comprising: a first two transistor inverter having the input electrodes of said two transistors connected to said input terminal and having the output electrodes of said two transistors coupled by first switch means to said output terminal, said first switch means being responsive to a first control input signal; and second switch means coupled between the output electrodes of said two transistors in said first inverter and said output terminal, said second swtich means being responsive to a second control input signal.
Claim 3
Dependent Claim
31 words
The amplifier circuit of claim 1 wherein the transistors in said first inverter and said first switch means employ relatively large transistors and said second switch means employs relatively small transistors.
Claim 4
Dependent Claim
12 words
The amplifier circuit of claim 2 wherein said transistors are CMOS devices.
Claim 5
Dependent Claim
33 words
The amplifier circuit of claim 3 wherein said first and second switch means each include a pair of complementary CMOS transistors respectively having their gates driven in complementary fashion by said control signals.
Claim 6
Dependent Claim
41 words
The amplifier circuit of claim 4 further including a resonant circuit coupled between said input annd output terminal whereby said circuit oscillates and said control signals are operated to produce the desired circuit function as determined by the frequency of oscillation.
Claim 7
Dependent Claim
33 words
The oscillator circuit of claim 5 further comprising a Schmitt trigger circuit having an input coupled to said oscillator output terminal thereby to provide a clean clock signal at the trigger circuit output.
References Cited (Backward Citations)
US4218661A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |