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US4965510A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated semiconductor circuit

Assignee: Siemens AG
•
Filing: 1989-01-17
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Granted: 1990-10-23
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Expires: 2009-01-17
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Abstract

Abstract Integrated semiconductor circuit, including a control loop including a first current source acting as an actual value transmitter for the control loop, and a final control element acting on the first current source as a control, the first current source being in the form of a current mirror having a plurality of transistors each forming an output part driving a respective load element, and a second constant current source being independent of the first current source and acting as a desired value transmitter for the control loop.

Inventors

  • 👤 Hans Kriedt
  • 👤 Andreas Dietze
  • 👤 Josef Fenk

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 17:56
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/22; G05F3/222

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 210 words
Integrated semiconductor circuit, comprising a control loop including a first current source acting as an actual value transmitter for said control loop, and final control means acting on said actual value transmitter as a control, said actual value transmitter being in the form of a current mirror having a plurality of transistors each forming an output part driving a respective load element, and a second constant current source being independent of said first current source and acting as a desired value transmitter for said control loop, wherein said current mirror of said actual value transmitter and said desired value transmitter each include first and second transistors of a given conductivity type having emitter-collector paths, said first transistor of said current mirror being connected as a diode, and said desired value transmitter and said actual value transmitter each includes a current mirror having third and fourth transistors of a conductivity type being opposite said given type and having emitter-collector paths, said third transistor of said current mirror of said desired value transmitter and said actual value transmitter being connected as a diode, the collector-emitter paths of said first and fourth transistors being connected together in series, and the collector-emitter paths of said second and third transistors being connected together in series.
Claim 2
Dependent Claim 210 words
Integrated semiconductor circuit, comprising a control loop including a first current source acting as an actual value transmitter for said control loop, and final control means acting on said actual value transmitter as a control, said actual value transmitter being in the form of a current mirror having a plurality of transistors each forming an output part driving a respective load element, and a second constant current source being independent of said first current source and acting as a desired value transmitter for said control loop, wherein said current mirror of said actual value transmitter and said desired value transmitter each include first and second transistors of a given conductivity type having emitter-collector paths, said first transistor of said current mirror being connected as a diode, and said desired value transmitter and said actual value transmitter each includes a current mirror having third and fourth transistors of a conductivity type being opposite said given type and having emitter-collector paths, said third transistor of said current mirror of said desired value transmitter and said actual value transmitter being connected as a diode, the collector-emitter paths of said first and fourth transistors being connected together in series, and the collector-emitter paths of said second and third transistors being connected together in series.

References Cited (Backward Citations)

US3962592A Cited
US4251743A Cited
JPS5671312A Cited
DE3146600A1 Cited
JPS58101310A Cited
US4475077A Cited
US4399399A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-10-22 1994-04-23 1994-10-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-10-22 1998-04-23 1998-10-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-10-22 2002-04-23 2002-10-23 $7700.00 Window Closed / Lapsed

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