US4965471A
Expired / Lapsed
US
⏱️ 0.0 years remaining
BI-CMOS clock driver with reduced crossover current
Assignee: Eastman Kodak Co
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Filing: 1989-06-26
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Granted: 1990-10-23
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Expires: 2009-06-26
Abstract
Abstract The present circuit is intended for use in providing CCD phase clocks. It has the benefit of reduced crossover currents which in turn reduces power consumption and device size requirements. The circuit is comprised of a pair of folded cascode CMOS amplifier input stages, a pair of bipolar output stages containing vertical NPN transistors, and 2 PMOS sense transistors for each output stage for reducing the crossover current which occurs when switching output stages. These sense transistors reduce the power consumption of the circuit and the size of the transistors necessary for the output. The input stage has the capability of operating from TTL or ECL signal inputs by selecting an input reference voltage. The folded cascode configuration also provides the level shifting necessary for inputs to the output stage's NPN transistors. The sense transistors provide feedback in the form of the charge stored in the output transistors to prevent a pair of output transistors from turning on prior to the other pair turning off.
Inventors
- 👤 Michael J. Gaboury
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 18:09
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/001; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K5/00; H03K5/15; H03K5/151
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
181 words
A BiCMOS clock driver circuit with reduced crossover current comprising: (a) a pair of amplifiers for receiving a differential input signal and for providing two pairs of complemented output signals; (b) sensing means including two pairs of sense transistors each one of the sense transistors of an associated pair connected to receive one of the a pair of complemented output signals from an associated one of said pair of amplifiers; and (c) output means including a pair of bipolar output stages each comprised of: a first pair of NPN transistors, serially connected to a source of potential, with the emitter of one transistor of each respective pair being connected to the collector of the other transistor to form an output connection, a second pair of NPN transistors each having an emitter connected to the bases of respective ones of said first pair of NPN transistors and with each of their collectors connectable to a source of potential and each of their bases coupled to said pair of amplifiers by a respective sense transistor so as to receive said complemented output signals.
Claim 2
Dependent Claim
181 words
A BiCMOS clock driver circuit with reduced crossover current comprising: (a) a pair of amplifiers for receiving a differential input signal and for providing two pairs of complemented output signals; (b) sensing means including two pairs of sense transistors each one of the sense transistors of an associated pair connected to receive one of the a pair of complemented output signals from an associated one of said pair of amplifiers; and (c) output means including a pair of bipolar output stages each comprised of: a first pair of NPN transistors, serially connected to a source of potential, with the emitter of one transistor of each respective pair being connected to the collector of the other transistor to form an output connection, a second pair of NPN transistors each having an emitter connected to the bases of respective ones of said first pair of NPN transistors and with each of their collectors connectable to a source of potential and each of their bases coupled to said pair of amplifiers by a respective sense transistor so as to receive said complemented output signals.
Claim 3
Dependent Claim
54 words
A clock driver circuit with reduced crossover current according to claim 1 and further comprising: two pairs of pull down transistors each connected to the base of a respective one of said first pair of NPN transistors and a source of potential and controlled by the complemented output signals from said pair of amplifiers.
Claim 4
Dependent Claim
108 words
A clock driver circuit with reduced crossover current comprising: (a) a pair of folded cascode CMOS amplifier input stages; (b) a pair of bipolar output stages each comprised of vertical NPN transistor driven by an associated one of said folded cascode CMOS amplifier input stages; and (c) sense transistors each connected to control the on and off state of an associated vertical NPN transistor and each cross coupled so as to be controlled by the state of a vertical NPN transistor in the other bipolar output stage such that only one vertical NPN transistor in each of said pair of bipolar output stages is conducting at any time.
Claim 5
Dependent Claim
108 words
A clock driver circuit with reduced crossover current comprising: (a) a pair of folded cascode CMOS amplifier input stages; (b) a pair of bipolar output stages each comprised of vertical NPN transistor driven by an associated one of said folded cascode CMOS amplifier input stages; and (c) sense transistors each connected to control the on and off state of an associated vertical NPN transistor and each cross coupled so as to be controlled by the state of a vertical NPN transistor in the other bipolar output stage such that only one vertical NPN transistor in each of said pair of bipolar output stages is conducting at any time.
Claim 6
Dependent Claim
60 words
A clock driver circuit with reduced crossover current according to claim 3 and further comprising: a pair of reference voltage input terminals coupled to said pair of folded cascode CMOS amplifier input stages for receiving a reference voltage having a magnitude that is selected to achieve a desired crossover between the off and on states of said vertical NPN transistors.
Claim 7
Dependent Claim
46 words
A clock driver circuit with reduced crossover current according to claim 3, wherein said pair of folded cascode CMOS amplifier input stages each provides as an output to said pair of output stages a pair of complementary control signals in response to a differential input signal.
References Cited (Backward Citations)
US4456837A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |