Thermal head printer

Claim 1

In a thermal head printer circuit comprising: a thermal print head mounted with a plurality of linearly arrayed dot print elements to which are connected print shift registers undergoing a clock-controlled shift scan and having therein a number of addresses corresponding to the number of dot elements, and a dot print signal generating circuit for outputting dot print signals when the number of clock pulses from a clock re-set for each scanning cycle equals the level of each of a series of input signals, said print head being adapted to effect for each shift shift scanning cycle simultaneous one-line dot printing of said dot print signals which are loaded and held in predetermined addresses of said print shift registers by shift-scanning, in combination, the improvement comprising: a plurality of serially connected delay shift registers undergoing a synchronous clock-controlled shift scan to which are inputted said dot print signals outputted from said dot print signal generating circuit, each such register having a number of addresses corresponding to the number of said dot print elements and being effective to output a plurality of consecutive time-delayed counterparts of each said dot print signal; and an OR gate to which are applied the time-delayed counterparts of said dot print signals outputted from said delay shift registers, and the current real-time dot print signal, wherein the cycle tune of time of the clock-controlled shift scanning operation of said shift registers is set according to the equation t≦T/(n+1), where T is the least print cycle sufficient to make said dot print elements normally responsive, and n is the number of said serially connected delay shift registers, the output signals of said OR gate being supplied to said print shift registers of said thermal print head.