Arbiter circuit for processing concurrent requests for access to shared resources

Claim 1

An arbiter circuit comprising: SR flip-flop means operable to provide signals to its two outputs in response to first and second request signals externally supplied thereto, said first and second request signals shiftable between first and second logic levels; sensing means to provide a sense output signal when said output signals from said two outputs of said flip-flop means reach simultaneously an intermediate level between said first and second logic levels; driver means operable in response to said sense output signal form said sensing means to positively drive one of said two output signals from said flip-flop to one of said first and second logic levels; and means for transferring said two output signals from said flip-flop means as first and second acknowledgement signals with a predetermined time delay, wherein said SR flip-flop means comprises first and second gate means, said first gate means is supplied with said first request signal and an output signal from said second gate means, said second gate means is supplied with said second request signal and an output signal from said first gate mans, said sensing means includes a third gate means supplied with the output signals from said first and second gate means and having a threshold level in the neighborhood of said intermediate level, said driver means comprises a voltage source for providing one of said first and second logic levels, and switching means connected between one of said two outputs of said SR flip-flop means and said voltage source and having a control terminal coupled to the output of said third gate means.