Nonvolatible capacitor random access memory

Claim 2

A DRAM cell having: (a) a storage gate, (b) a nonvolatile dielectric stack under and contiguous to said storage gate for storing electrical charge, (c) a region of semiconductor material spaced from said storage gate having a heavily doped n+-type annular region therein, said storage gate disposed over the central portion of said annular region and extending over a portion of said annular region, said n+-type region having a doping concentration in the range from about 1×10 18 ions/cc to about 1×10 21 ions/cc and an n-type tank has a doping concentration in the range from about 1×10 15 ions/cc to about 1×10 16 ions/cc, and (d) said n-type tank disposed in said region of semiconductor material beneath and contiguous to said nonvolatile dielectric stack and electrically coupled to and within said central portion of said annular region.

Claim 3

The cell of claim 1 wherein said tank extends beneath and below a portion of said annular region and spans said storage gate.

Claim 4

A DRAM cell as set forth in claim 1 wherein said annular region completely surrounds said storage gate.

Claim 5

A DRAM cell as set forth in claim 3 further including a bit control line connectable to said n type tank and a transfer gate causing connection of said bit control line to said n type tank.

Claim 6

A memory array which comprises a plurality of cells as set forth in claim 4, electrically arranged in rows and columns, each said transfer gate having a gate electrode, a source and a drain, a bit control line coupled to one of the source and drain of each said transfer gate, a word control line coupled to said gate electrode of each said transfer gate and a storage gate control line coupled to said storage gate.

Claim 7

The cell of claim 3 wherein said tank extends beneath and below a portion of said annular region and spans said storage gate.

Claim 8

A DRAM cell as set forth in claim 1 further including a bit control line connectable to said n type tank and a transfer gate causing connection of said bit control line to said n type tank.

Claim 9

A DRAM as set forth in claim 7 wherein said transfer gate includes gate, source and drain electrodes, said bit control line being coupled to one of said source and drain electrodes, a word control line coupled to said gate electrode and a column control line coupled to said storage gate.

Claim 10

A memory array which comprises a plurality of cells as set forth in claim 8, electrically arranged in rows and columns, each said transfer gate having a gate electrode, a source and a drain, a bit control line coupled to one of the source and drain of each said transfer gate, a word control line coupled to said gate electrode of each said transfer gate and a storage gate control line coupled to said storage gate.

Claim 11

A memory array which comprises a plurality of cells as set forth in claim 7, electrically arranged in rows and columns, each said transfer gate having a gate electrode, a source and a drain, a bit control line coupled to one of the source and drain of each said transfer gate, a word control line coupled to said gate electrode of each said transfer gate and a storage gate control line coupled to said storage gate.

Claim 12

The array of claim 10 wherein said tank extends beneath and below a portion of said annular region and spans said storage gate.

Claim 13

A memory array which comprises a plurality of DRAM cells electrically arranged in rows and columns, each cell having: (a) a storage gate, (b) a nonvolatile charge storing layer thereunder for storing electrical charge, (c) a substrate having a heavily doped n+ type ring region therein surrounding said storage gate and extending under said charge storing layer, and (d) an n-type tank disposed in said substrate beneath said nonvolatile charge storing layer and electrically connected to said n+ type ring region, (e) further including a bit control line connectable to said n-type tank and a transfer gate causing connection of said bit control line to said n-type tank, (f) each said transfer gate having a gate electrode, a source and a drain, a bit control line coupled to one of the source and drain of each said transfer gate, a word line coupled to said gate electrode of each said transfer gate and a storage gate control line coupled to said storage gate, (g) further including plural sense-refresh amplifiers, each coupled to two said bit control lines and one said storage gate control line and MOSFET means coupled between each said amplifier and the associated bit and storage gate control lines for selectively isolating and connecting said lines to said amplifiers.

Claim 14

A memory array which comprises a plurality of DRAM cells electrically arranged in rows and columns, each cell having: (a) a storage gate, (b) a nonvolatile charge storing layer thereunder for storing electrical charge, (c) a substrate having a heavily doped n+ type ring region therein surrounding said storage gate and extending under said charge storing layer, and (d) an n-type tank disposed in said substrate beneath said nonvolatile charge storing layer and electrically connected to said n+ type ring region, (e) further including a bit control line connectable to said n-type tank and a transfer gate causing connection of said bit control line to said n-type tank, (f) each said transfer gate having a gate electrode, a source and a drain, a bit control line coupled to one of the source and drain of each said transfer gate, a word line coupled to said gate electrode of each said transfer gate and a storage gate control line coupled to said storage gate, (g) further including plural sense-refresh amplifiers, each coupled to two said bit control lines and one said storage gate control line and MOSFET means coupled between each said amplifier and the associated bit and storage gate control lines for selectively isolating and connecting said lines to said amplifiers.

Claim 15

A memory array as set forth in claim 12, wherein each said n-type ring has a doping concentration in the range from about 1×10 18 ions/cc to about 1×10 21 ions/cc and said n-type tank has a doping concentration in the range from about 1×10 15 ions/cc to about 1×10 6 ions/cc.

Claim 16

A memory array as set forth in claim 13 wherein each said ring completely surrounds said storage gate.

Claim 17

A memory array as set forth in claim 14 wherein each said n+ region extends beneath said nonvolatile charge storing region.

Claim 18

A memory array which comprises a plurality of DRAM cells electrically arranged in rows and columns, each cell having: (a) a storage gate, (b) a nonvolatile charge storing layer thereunder for storing electrical charge, (c) a substrate having a heavily doped n+ type ring region therein surrounding said storage gate and extending under said charge storing layer, and (d) an n-type tank disposed in said substrate beneath said nonvolatile charge storing layer and electrically connected to said n+ type ring region, (e) further including a bit control line connectable to said n-type tank and a transfer gate causing connection of said bit control line to said n-type tank, (f) each said transfer gate having a gate electrode, a source and a drain, a bit control line coupled to one of the source and drain of each said transfer gate, a word line coupled to said gate electrode of each said transfer gate and a storage gate control line coupled to said storage gate, (g) further including means for turning on said transfer gate to charge said stack from said bit line, for then turning off said transfer gate responsive to a change of voltage on said bit control line to float said bit line and for then turning on said transfer gate to charge said stack from said floating bit line.

Claim 19

A memory array which comprises a plurality of DRAM cells electrically arranged in rows and columns, each cell having: (a) a storage gate, (b) a nonvolatile charge storing layer thereunder for storing electrical charge, (c) a substrate having a heavily doped n+ type ring region therein surrounding said storage gate and extending under said charge storing layer, and (d) an n-type tank disposed in said substrate beneath said nonvolatile charge storing layer and electrically connected to said n+ type ring region, (e) further including a bit control line connectable to said n-type tank and a transfer gate causing connection of said bit control line to said n-type tank, (f) each said transfer gate having a gate electrode, a source and a drain, a bit control line coupled to one of the source and drain of each said transfer gate, a word line coupled to said gate electrode of each said transfer gate and a storage gate control line coupled to said storage gate, (g) further including means for turning on said transfer gate to charge said stack from said bit line, for then turning off said transfer gate responsive to a change of voltage on said bit control line to float said bit line and for then turning on said transfer gate to charge said stack from said floating bit line.

Claim 20

The array of claim 16 wherein said tank extends beneath and below a portion of said ring and spans said storage gate.

Claim 21

A memory array as set forth in claim 16, further including plural sense-refresh amplifiers, each coupled to two said bit control lines and one said storage gate control line and MOSFET means coupled between each said amplifier and the associated bit and storage gate control lines for selectively isolating and connecting said lines to said amplifiers.