GaAs FET manufacturing process employing channel confining layers

Claim 1

A reliably repeatable high volume manufacturing process for high speed GaAs FETs comprising: providing, by MOCVD, a first undoped layer of AlGaAs on a selected foundation; providing, by MOCVD, an undoped layer of GaAs on said first layer of AlGaAs; providing, by MOCVD, a second undoped layer of AlGaAs on said layer of GaAs; defining a channel region in said layer of GaAs and implanting silicon through said second layer of AlGaAs and into said layer of GaAs; providing a TiWN layer over said second layer of AlGaAs; forming an etch mask over said TiWN layer, said etch mask defining a gate pattern; overetching to provide a gate having a length shorter than the gate length defined by said etch mask; implanting silicon through said second AlGaAs layer and into said GaAs layer to form source and drain regions employing said etch mask as an implant masking element to self-align said source region with said gate; providing source and drain electrodes by a process sequence including a heating step to sinter said electrodes at a temperature of between about 800° C. and 850° C., said heating step serving to activate said implanted source, drain and channel regions, whereby separate activation anneals for said implanted regions are not required.