US4961184A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrate and hold amplifier
Assignee: A T & E Corp A DE CORP
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Filing: 1989-01-31
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Granted: 1990-10-02
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Expires: 2009-01-31
Abstract
Abstract The present invention relates to a system which uses information in a certain band of frequencies, f b . The information of interest is contained in an analog signal that has noise at higher frequencies. The analog signal is sampled using an integrate and hold amplifier, hence, noise from higher frequencies is aliased into the region of interest f b . In accordance with the present invention, the integrated and hold amplifier has a frequency response which has a zero at a frequency, f n , which is one of the frequencies aliased into the band of frequencies f b . Thus, the effect of the noise that appears near the frequency f n has much less effect on the signal when it is aliased into the frequency band of interest, f b . The performance of the system is thereby improved.
Inventors
- 👤 Jeffrey R. Owen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:08
CPC Classifications
H; H03; H03D; H03D1/00; H03D1/02; H03D1/04; H03D3/00; H03D3/001; H03D3/002
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
80 words
A system including in combination: means for receiving an analog signal which has a data signal component located in a relatively narrow frequency band, an integrate and hold circuit which samples said data signal, said integrate and hold circuit having an integrate time such that the frequency response of said integrate and hold circuit has a zero located at a frequency which is aliased into said relatively narrow frequency band, whereby interference due to noise from higher frequencies is minimized.
Claim 2
Independent Claim
80 words
A system including in combination: means for receiving an analog signal which has a data signal component located in a relatively narrow frequency band, an integrate and hold circuit which samples said data signal, said integrate and hold circuit having an integrate time such that the frequency response of said integrate and hold circuit has a zero located at a frequency which is aliased into said relatively narrow frequency band, whereby interference due to noise from higher frequencies is minimized.
Claim 3
Dependent Claim
46 words
The system in accordance with claim 1 wherein said integrate and hold circuit comprises: (a) an analog switch for controlling an integration cycle; (b) an amplifier subcircuit operatively connected to said analog switch; and (c) a resistor connected between said analog switch and said amplifier subcircuit.
Claim 4
Dependent Claim
27 words
The system in accordance with claim 2 wherein said amplifier subcircuit comprises an amplifier, a capacitor and a capacitor discharge switch connected in parallel with one another.
Claim 5
Dependent Claim
36 words
The system in accordance with claim 3 wherein said integrate and hold circuit further comprises: (d) timing and control means operatively connected to said analog switch and to said capacitor discharge switch for controlling operation thereof.
Claim 6
Dependent Claim
25 words
The system in accordance with claim 4 wherein said integrate and hold circuit further comprises: (e) an analog-to-digital converter operatively connected to said amplifier subcircuit.
Claim 7
Dependent Claim
24 words
The integrate and hold circuit in accordance with claim 5 wherein operation of said analog-to-digital converter is controlled by said timing and control means.
Claim 8
Dependent Claim
94 words
An integrate and hold amplifier for reducing signal interference at a region of interest comprising: (a) an analog switch for controlling the duration of an integration cycle; (b) an amplifier subcircuit operatively connected to said analog switch, said subcircuit comprising an amplifier, a capacitor and a capacitor discharge switch connected in parallel with one another; (c) a resistor connected between said analog switch and said amplifier subcircuit; and (d) said integration cycle being timed to produce a zero response of said integrate and hold amplifier at a predetermined frequency to eliminate signal interference thereat.
Claim 9
Dependent Claim
94 words
An integrate and hold amplifier for reducing signal interference at a region of interest comprising: (a) an analog switch for controlling the duration of an integration cycle; (b) an amplifier subcircuit operatively connected to said analog switch, said subcircuit comprising an amplifier, a capacitor and a capacitor discharge switch connected in parallel with one another; (c) a resistor connected between said analog switch and said amplifier subcircuit; and (d) said integration cycle being timed to produce a zero response of said integrate and hold amplifier at a predetermined frequency to eliminate signal interference thereat.
Claim 10
Dependent Claim
33 words
The integrate and hold amplifier in accordance with claim 7, further comprising: (e) timing and control means operatively connected to said analog switch and to said capacitor discharge switch for controlling operation thereof.
Claim 11
Dependent Claim
22 words
The integrate and hold amplifier in accordance with claim 8, further comprising: (f) an analog-to-digital converter operatively connected to said amplifier subcircuit.
Claim 12
Dependent Claim
24 words
The integrate and hold amplifier in accordance with claim 9 wherein operation of said analog-to-digital converter is controlled by said timing and control means.
Claim 13
Independent Claim
98 words
A system including: an analog signal which has a data signal component located in a relatively narrow frequency band, an integrate and hold circuit which samples said data signal to generate a second analog signal, said integrate and hold circuit having an integrate time which produces a frequency response with a zero located at a frequency which is aliased into said relatively narrow frequency band, an analog to digital converter to convert said second analog signal to a digital signal, and means for digitally processing said digital signal, whereby interference due to noise from higher frequencies is minimized.
Claim 14
Independent Claim
98 words
A system including: an analog signal which has a data signal component located in a relatively narrow frequency band, an integrate and hold circuit which samples said data signal to generate a second analog signal, said integrate and hold circuit having an integrate time which produces a frequency response with a zero located at a frequency which is aliased into said relatively narrow frequency band, an analog to digital converter to convert said second analog signal to a digital signal, and means for digitally processing said digital signal, whereby interference due to noise from higher frequencies is minimized.
Claim 15
Dependent Claim
28 words
The subsystem for reducing signal interference in accordance with claims 11 wherein a noise signal that causes the most significant interference is disposed in a second frequency interval.
Claim 16
Dependent Claim
24 words
The subsystem for reducing signal interference in accordance with claim 12 wherein a frequency region of interest, f r , is approximately 66.5 kHz.
Claim 17
Dependent Claim
19 words
The subsystem for reducing signal interference in accordance with claim 13 wherein a sampling rate is approximately 133 kHz.
Claim 18
Dependent Claim
62 words
In a system with a continuous time signal input, a method for reducing signal interference comprising the steps of: sampling said continuous time signal at a predetermined sampling rate, coordinating sampling rate and integration time such that frequency response has a zero value at frequencies that are aliased into a region of interest due to the effects of sampling, thereby reducing interference.
Claim 19
Dependent Claim
62 words
In a system with a continuous time signal input, a method for reducing signal interference comprising the steps of: sampling said continuous time signal at a predetermined sampling rate, coordinating sampling rate and integration time such that frequency response has a zero value at frequencies that are aliased into a region of interest due to the effects of sampling, thereby reducing interference.
References Cited (Backward Citations)
US4039979A
Cited
US4322697A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-01 | 1994-04-02 | 1994-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-01 | 1998-04-02 | 1998-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-01 | 2002-04-02 | 2002-10-02 | $7700.00 | Window Closed / Lapsed |