US4961131A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable controller
Assignee: Toshiba Corp
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Filing: 1988-04-20
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Granted: 1990-10-02
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Expires: 2008-04-20
Abstract
Abstract A programmable controller includes a master CPU for processing data in accordance with a predetermined program including a prescribed sequence of operating steps, a plurality of operating devices responsive to the master CPU, each having at least two operating states, a monitor device for displaying the execution state of a predetermined number of steps in response to batch processing by the master CPU, and a slave CPU. The slave CPU includes a command execution circuit for generating command output information in response to the execution of each operating step, a register for storing the command output information and the operating state of selected operating devices, and a counter for counting the predetermined number of executed operating steps in the sequence of the program.
Inventors
- 👤 Kazuhide Ashida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:50
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G05B19/058
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
178 words
A programmable controller, comprising: a master CPU for processing data in accordance with a predetermined program including a prescribed sequence of operating steps; a plurality of operating devices responsive to the master CPU, each having at least two operating states; a slave CPU, operatively coupled to the master CPU and including command execution circuit means for generating command ouput information in response to the execution of each operating step; register means, operatively coupled to the command execution circuit means, for storing the command output information and the operating state of selected operating devices; counting means, operatively coupled to the command execution circuit means and the master CPU, for counting a predetermined number of executed operating steps in the sequence of the program in response to the command output information from the command execution circuit means, and for providing an output signal to the master CPU upon counting up to the predetermined number of executed operating steps; and monitor means, responsive to processing performed by the master CPU, for displaying the execution state of the predetermined number of steps.
Claim 2
Dependent Claim
178 words
A programmable controller, comprising: a master CPU for processing data in accordance with a predetermined program including a prescribed sequence of operating steps; a plurality of operating devices responsive to the master CPU, each having at least two operating states; a slave CPU, operatively coupled to the master CPU and including command execution circuit means for generating command ouput information in response to the execution of each operating step; register means, operatively coupled to the command execution circuit means, for storing the command output information and the operating state of selected operating devices; counting means, operatively coupled to the command execution circuit means and the master CPU, for counting a predetermined number of executed operating steps in the sequence of the program in response to the command output information from the command execution circuit means, and for providing an output signal to the master CPU upon counting up to the predetermined number of executed operating steps; and monitor means, responsive to processing performed by the master CPU, for displaying the execution state of the predetermined number of steps.
Claim 3
Dependent Claim
32 words
The controller of claim 1, wherein the register means includes status register means for storing the operating state of the operating devices, and result register means for storing the command output information.
Claim 4
Dependent Claim
42 words
The controller of claim 1, wherein the monitor means includes monitor display means for displaying a prescribed monitor view showing the execution state of the operating steps, and monitor interface means for controlling the monitor view in response to the master CPU.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-01 | 1994-04-02 | 1994-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-01 | 1998-04-02 | 1998-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-01 | 2002-04-02 | 2002-10-02 | $7700.00 | Window Closed / Lapsed |