Digital transmission demodulator including an automatic fault corrector

Claim 2

A demodulator for digital transmission using the technique known per se of transposing the signal to baseband and comprising separator means for operating a received HF signal into first and second identical auxiliary signals, a local oscillator providing an in-phase output signal and a quadrature output signal at 90° to its in-phase output signal, a first mixer for transposing the first auxiliary signal into an in-phase base component by multiplying it with the in-phase output signal from the local oscillator, a second mixer for transposing the second auxiliary signal into a quadrature base component by multiplying it with the quadrature output signal from the local oscillator, and respective filter and amplifier means and analog-to-digital converters connected to the outputs from each of the mixers, wherein the demodulator further includes: estimation means suitable for estimating faults on groups of samples Y p ,k, Y q ,k taken from the outputs of the analog-to-digital converters, faults being estimated in the form of five parameters, namely: the corrective gain α to be applied to the in-phase channel, the corrective gain β to be applied to the quadrature channel, the voltage offset a on the in-phase channel, the voltage offset b on the quadrature channel, and phase error δθ relative to true quadrature; and correction means for correcting the current samples Y p , Y q , on the basis of the parameters estimated on an earlier group of samples.

Claim 3

A demodulator according to claim 1, wherein the corrected samples Z p ,n and Z q ,n are established on the basis of the following equations: Z.sub.p,n =α(Y.sub.p,n -a)+β(Y.sub.p,n -b)·sin δθ (7) Z.sub.q,n =β(Y.sub.q,n -b)·cos δθ(8) in which: α=the corrective gain to be applied to the in-phase channel; β=the corrective gain to be applied to the quadrature channel; a=the voltage offset on the in-phase channel; b=the voltage offset on the quadrature channel; δθ=the phase error relative to true quadrature; Y p ,n =current samples on the in-phase channel prior to correction; and Y q ,n =current samples on the quadrature channel prior to correction.

Claim 4

A demodulator according to claim 1, wherein the parameter a representing the voltage offset on the in-phase channel is obtained by taking the average of the samples Y p ,k on the in-phase channel using the equation: ##EQU8##

Claim 5

A demodulator according to claim 1, wherein the parameter b representing the voltage offset on the quadrature channel is obtained by taking the average of the samples Y q ,k on the quadrature channel using the equation: ##EQU9##

Claim 6

A demodulator according to claim 1, wherein the parameter α representative of the corrective gain to be applied to the in-phase channel is obtained using the equation: ##EQU10##

Claim 7

A demodulator according to claim 1, wherein the parameter β representative of the corrective gain to be applied to quadrature channel is determined using the equation: ##EQU11##

Claim 8

A demodulator according to claim 1, wherein the ratio α/β of the corrective gains to be applied to the in-phase channel and the quadrature channel is obtained by the root mean square of the differences (Y p ,k -a) and (Y q ,k -b), i.e. on the basis of the equation: ##EQU12##

Claim 9

A demodulator according to claim 1, wherein the parameter δθ representative of phase error relative to true quadrature is estimated on the basis of the equation: ##EQU13##

Claim 10

A demodulator according to claim 1, wherein the estimation means include a microprocessor.

Claim 11

A demodulator according to claim 1, wherein the correction means are constituted by hard-wired logic.

Claim 12

A demodulator according to claim 1, wherein the estimation means deliver some of the estimated parameters in the form of logarithms, and the correction means include adders.

Claim 13

A demodulator according to claim 1, wherein the correction means include memories for transforming numbers into their logarithms, and memories for performing the inverse transformation.

Claim 14

A demodulator according to claim 1, wherein the correction means include readback bistables enabling signals to be synchronized.

Claim 15

A demodulator according to claim 1, wherein the correction means comprise the following digital components: a first set of bistables receiving the parameter a representing the voltage offset on the in-phase channel; a second set of bistables receiving the parameter b representing the voltage offset on the quadrature channel; a third set of bistables receiving the logarithm of the parameter α representative of the corrective gain to be applied to the in-phase channel; a fourth set of bistables receiving the logarithm of the parameter β representative of the corrective gain to be applied to the quadrature channel; a fifth set of bistables receiving the logarithm of the sine of the parameter δθ representative of the phase error relative to true quadrature; a sixth set of bistables receiving the logarithm of the cosine of the parameter δθ representative of phase error; a first adder having its inputs connected to receive the current samples Y p on the in-phase channel and the signal from the first set of bistables; a first memory converting the output signal from the first adder into the logarithm thereof; a seventh set of bistables connected to the output of the first memory; a second adder having its inputs connected to receive the signals from the third and seventh sets of bistables; a third adder having its inputs connected to receive the current samples Y q on the quadrature channel and the signal from the second set of bistables; a second memory converting the output signal from the third adder into its logarithm; an eighth set of bistables connected to the output from the second memory; a fourth adder having its inputs connected to receive the signals from the fourth and eighth sets of bistables; a fifth adder having its inputs connected to receive the signals from the fifth set of bistables and from the fourth adder; a sixth adder having its inputs connected to receive the signals from the sixth set of bistables and from the fourth adder; a ninth set of bistables connected to the output from the second adder; a third memory for providing the antilogarithm of the signal delivered by the ninth set of bistables; a tenth set of bistables connected to the output from the fifth adder; a fourth memory for taking the antilogarithm of the signal delivered by the tenth set of bistables; a seventh adder having its inputs connected to receive the signals from the third and fourth memories and delivering corrected samples Z p at its output; an eleventh set of bistables connected to the output from the sixth adder; and a fifth memory providing the antilogarithm of the signal delivered by the eleventh set of bistables and delivering corrected samples Z q at its output.