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US4959328A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for manufacturing a semiconductor component contactable on both sides

Assignee: Licentia Patent Verwaltungs GmbH
•
Filing: 1988-05-27
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Granted: 1990-09-25
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Expires: 2008-05-27
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Abstract

Abstract A method for manufacturing semiconductor components contactable on both sides, in particular IMPATT diodes. The active silicon layers of the IMPATT diode are grown onto a silicon substrate. The first silicon layer grown onto the silicon substrate has a high boron/germanium doping level and acts as an etch atop layer when the substrate is removed. The boron/germanium doping of the first silicon layer compensates for the mechanical stress in the silicon layer generated by the boron doping.

Inventors

  • 👤 Wolfgang Behr
  • 👤 Johann-Friedrich Luy
  • 👤 Karl Strohm

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 11:34
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/644; H10D; H10D62/00; H10D62/80; H10D62/83; H10D62/834; H10D8/00; H10D8/40; Y; Y10; Y10S; Y10S438/00; Y10S438/977

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 120 words
A method of manufacturing a semiconductor component which is contacted on both sides comprising the steps of: providing a silicon substrate; epitaxially growing a sequence of differently doped silicon semiconductor layers, corresponding to the layer sequence of the semiconductor component, on a surface of said substrate with the first silicon semiconductor layer of said sequence directly grown on said surface of said substrate being a p + -doped silicon layer which is doped with boron, of a concentration in excess of 7×10 19 cm -3 , and germanium of a concentration sufficient to compensate for mechanical stresses generated by the boron; removing said substrate by etching; contacting said first layer; and, contacting the last layer of said sequence of layers.
Claim 2
Independent Claim 120 words
A method of manufacturing a semiconductor component which is contacted on both sides comprising the steps of: providing a silicon substrate; epitaxially growing a sequence of differently doped silicon semiconductor layers, corresponding to the layer sequence of the semiconductor component, on a surface of said substrate with the first silicon semiconductor layer of said sequence directly grown on said surface of said substrate being a p + -doped silicon layer which is doped with boron, of a concentration in excess of 7×10 19 cm -3 , and germanium of a concentration sufficient to compensate for mechanical stresses generated by the boron; removing said substrate by etching; contacting said first layer; and, contacting the last layer of said sequence of layers.
Claim 3
Dependent Claim 18 words
A method according to claim 1, wherein an anisotropic etch is used to remove the silicon semiconductor substrate.
Claim 4
Dependent Claim 14 words
A method according to claim 1, wherein the semiconductor component is an IMPATT diode.
Claim 5
Dependent Claim 28 words
A method as defined in claim 1 wherein said boron concentration is approximately 1.3×10 20 atoms/cm 3 and said germanium concentration is approximately 1.4×10 21 atoms/cm 3 .
Claim 6
Dependent Claim 64 words
A method as defined in claim 1 wherein: said semiconductor component is a doubled drift IMPATT diode; said step of epitaxially growing includes sequentially growing a p-doped silicon layer, an n-doped silicon layer and an n + -doped silicon layer on said first p + -doped silicon layer; and said step of contacting the last layer includes contacting said n + -doped silicon layer.
Claim 7
Dependent Claim 73 words
A method as defined in claim 1 wherein: said semiconductor component is a Quasi-Read double drift IMPATT diode; said step of epitaxially growing includes sequentially growing a p-doped silicon layer, a relatively thin n + -doped silicon layer, an n-doped silicon layer and an n + -doped silicon layer on said first p + -doped silicon layer; and said step of contacting the last layer includes contacting said n + -doped silicon layer.
Claim 8
Dependent Claim 44 words
A method as defined in claim 1 wherein said step of contacting the last layer of said layer sequences is carried out prior to said step of removing, and said step of contacting said first layer is carried out after said step of removing.

References Cited (Backward Citations)

EP0029334A1 Cited
EP0167948A2 Cited
DE3425063A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-09-24 1994-03-26 1994-09-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-09-24 1998-03-26 1998-09-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-09-24 2002-03-26 2002-09-25 $7700.00 Window Closed / Lapsed

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