System with a N stages timing silo and P stages information silo for soloing information

Claim 2

An arrangement for siloing information in a computer system generating said information and a series of bits, the arrangement comprising: a timing silo having an interger number n of timing state devices forming a set sequentially connected for receiving and siloing said series of bits wherein at least one of said bits is an enabling bit; an information silo having an integer number p of information state devices forming a set sequentially connected for receiving and siloing said information, said information state devices having device enables coupled to different locations in said timing silo wherein each said different location is separated from another one of said different locations by a plurality of said timing state devices such that said enabling bit at a particular location in said timing silo enables said information state device which is coupled to said particular location to receive said information from a previous information state device; and wherein p is greater than one and is equal to or less than one half the value of n.

Claim 3

The arrangement of claim 1, wherein said information is a write command and its context and one of said bits is a command bit which indicates a new command has issued.

Claim 4

The arrangement of claim 1, wherein the number n is equal to twice a maximum number of cycles said information is to be siloed.

Claim 5

The arrangement of claim 3, wherein n is equal to 40.

Claim 6

The arrangement of claim 4, wherein p is equal to: one plus.

Claim 7

The arrangement of claim 5, wherein p is 4.

Claim 8

The arrangement of claim 6, wherein the device enable of a first said information state device is coupled to an input of a first said timing state device, and the device enables of successive said information state devices are separately coupled to outputs of different timing state devices in said timing silo.

Claim 9

The arrangement of claim 6, wherein the device enable of a first said information state devices is coupled to an input of a first said timing state devices in said timing silo, the device enable of a second said information state devices is coupled to an output of an eleventh said timing state devices in said timing silo, the device enable of a third said information state devices is coupled to an output of a twenty-second said timing state device in said timing silo, and a fourth said information state devices is coupled to an output of a thirty-first said timing state device

Claim 10

The arrangement of claim 8, further comprising a first write command line coupled to an output of a thirty-second said timing state device for carrying a first start signal, and a second write command line coupled to an output of a fortieth said timing state device for carrying a second start signal.

Claim 11

The arrangement of claim 1, wherein said timing state devices are timing latches and said information state devices are information latches.

Claim 12

A vector processor comprising: vector registers for storing data; a first logic unit coupled to said vector registers, said first logic unit sending logical results to said vector register an integer number q cycles after receiving input rom said vector registers; a second logic unit coupled to said vector registers, said second logic unit sending multiplication results to said vector registers an integer number x cycles after receiving input form said vector registers; a vector controller coupled to said vector registers and to said first and second logic units, said vector controller generating information for a particular command concurrently with said vector registers sending operands to one of said first and second logic units corresponding to said particular command; a timing silo coupled to said vector controller having an interger number n of timing state devices forming a set sequentially connected for receiving and siloing a series of bits from said vector controller wherein at least one of said bits is an enabling bit; and an information silo coupled between said vector controller and said vector registers having an integer number p of information state devices forming a set sequentially connected for receiving and siloing information from said vector controller, said p information state devices having device enables coupled to different locations in said timing silo wherein each said different location is separated from another one of said different locations by a plurality of said timing state devices such that said enabling bit at a particular location in said timing silo enables one of said p information state devices which is coupled to said particular location to receive said information from a previous information state device, wherein p is greater than one and is equal to or less than one half the value of n.

Claim 13

A vector processor comprising: vector registers for storing data; a first logic unit coupled to said vector registers, said first logic unit sending logical results to said vector register an integer number q cycles after receiving input rom said vector registers; a second logic unit coupled to said vector registers, said second logic unit sending multiplication results to said vector registers an integer number x cycles after receiving input form said vector registers; a vector controller coupled to said vector registers and to said first and second logic units, said vector controller generating information for a particular command concurrently with said vector registers sending operands to one of said first and second logic units corresponding to said particular command; a timing silo coupled to said vector controller having an interger number n of timing state devices forming a set sequentially connected for receiving and siloing a series of bits from said vector controller wherein at least one of said bits is an enabling bit; and an information silo coupled between said vector controller and said vector registers having an integer number p of information state devices forming a set sequentially connected for receiving and siloing information from said vector controller, said p information state devices having device enables coupled to different locations in said timing silo wherein each said different location is separated from another one of said different locations by a plurality of said timing state devices such that said enabling bit at a particular location in said timing silo enables one of said p information state devices which is coupled to said particular location to receive said information from a previous information state device, wherein p is greater than one and is equal to or less than one half the value of n.

Claim 14

The arrangement of claim 11, further comprising an address generator coupled to the timing silo and the information silo for receiving said siloed information and generating write addresses.

Claim 15

The arrangement of claim 12, wherein said information is a write command and its context and one of said bits is a command bit which indicates a new command has issued.

Claim 16

The arrangement of claim 11, wherein the number n is equal to twice a maximum number of cycles said information is to b siloed.

Claim 17

The arrangement of claim 14, wherein n is equal to 40.

Claim 18

The arrangement of claim 15, wherein p is equal to: one plus.

Claim 19

The arrangement of claim 16, wherein p is 4.

Claim 20

The arrangement of claim 17, wherein the device enable of a first said information state device is coupled to an input of a first said timing state device in said timing silo, the device enable of a second said information state device is coupled to an output of an eleventh said timing state device in said timing silo, the device enable of a third said information state device is coupled to an output of a twenty-second said timing state device in said timing silo, and the device enable of a fourth said information state device is coupled to an output of a thirty-first said timing state device.

Claim 21

The arrangement of claim 18, further comprising a first write command line coupled to an output of a thirty-second said timing state device for carrying a first start signal, and a second write command line coupled to an output of a fortieth said timing state device for carrying a second start signal.

Claim 22

The arrangement of claim 11, wherein said information is a write command and its context and one of said bit is a command bit which indicates a new command has issued.