Image processing apparatus

Claim 2

An image processing apparatus of parallel processing type using DDA method for processing image data, the apparatus comprising: input interfacee means for feeding image data to be contracted as series of predetermined number of bits; DDA means for generating DDA bit pattern indicating valid bits in the series according to a given contraction rate; correction means for detecting those series which are fractional as a series of predetermined number of bits, and generating correction bit pattern indicating validity of last bits of the series which are fractional as a series of predetermined number of bits; means for producing valid bit pattern indicating valid bits in the image data as the series of predetermined number of bits, in accordance with the DDA bit pattern and the correction bit pattern; and means for performing contraction of the image data in accordance with the valid bit pattern.

Claim 3

The apparatus of claim 1, wherein the correction means generates the correction bit pattern only when the image data are not fractional as a series of predetermined number of bits, and wherein the producing means produces the valid bit pattern in accordance with the DDA bit pattern only when the image data are not fractional as a series of predetermined number of bits.

Claim 4

The apparatus of claim 1, wherein the producing means comprises plurality of OR gates which output OR of the DDA bit pattern and the correction bit pattern as the valid bit pattern.

Claim 5

An image processing apparatus of parallel processing type using DDA method for processing image data, the apparatus comprising: memory means for memorizing the image data; input interface means for feeding a portion of the image data, extracted from the image data in the memory means, which are to be contracted, as series of predetermined number of bits starting from top of the image data in the memory means; DDA means for generating DDA bit pattern indicating valid bits in the series according to a given contraction rate; correction means for detecting those series which are fractional as a series of predetermined number of bits starting from top of the extracted image data, and generating correction bit pattern indicating validity of last bits of the series which are fractional as a series of predetermined number of bits; means for producing valid bit pattern indicating valid bits in the image data as the series of predetermined number of bits, in accordance with the DDA bit pattern and the correction bit pattern; and means for performing contraction of the extracted portion of the image data in accordance with the valid bit pattern.

Claim 6

An image processing apparatus of parallel processing type using DDA method for processing image data, the apparatus comprising: memory means for memorizing the image data; input interface means for feeding a portion of the image data, extracted from the image data in the memory means, which are to be contracted, as series of predetermined number of bits starting from top of the image data in the memory means; DDA means for generating DDA bit pattern indicating valid bits in the series according to a given contraction rate; correction means for detecting those series which are fractional as a series of predetermined number of bits starting from top of the extracted image data, and generating correction bit pattern indicating validity of last bits of the series which are fractional as a series of predetermined number of bits; means for producing valid bit pattern indicating valid bits in the image data as the series of predetermined number of bits, in accordance with the DDA bit pattern and the correction bit pattern; and means for performing contraction of the extracted portion of the image data in accordance with the valid bit pattern.

Claim 7

The apparatus of claim 4, wherein the correction means generates the correction bit pattern only when the image data are not fractional as a series of predetermined number of bits, and wherein the producing means produces the valid bit pattern in accordance with the DDA bit pattern only when the image data are not fractional as a series of predetermined number of bits.

Claim 8

The apparatus of claim 4, wherein the producing means comprises plurality of OR gates which output OR of the DDA bit pattern and the correction bit pattern as the valid bit pattern.

Claim 9

An image processing apparatus of parallel processing type using DDA method for processing image data, the apparatus comprising: memory means for memorizing the image data as first series of first predetermined number of bits; input interface means for feeding a portion of the image data, extracted from the image data in the memory means, which are to be contracted, as second series of second predetermined number of bits; DDA means for generating DDA bit pattern indicating valid bits in the second series according to a given contraction rate; correction means for detecting those second series which are fractional as a second series of second predetermined number of bits, and generating correction bit pattern indicating validity of last bits of the second series which are fractional as a second series of second predetermined number of bits; means for producing valid bit pattern indicating valid bits in the image data as the second series of second predetermined number of bits, in accordance with the DDA bit pattern and the correction bit pattern; and means for performing contraction of the extracted portion of the image data in accordance with the valid bit pattern.

Claim 10

An image processing apparatus of parallel processing type using DDA method for processing image data, the apparatus comprising: memory means for memorizing the image data as first series of first predetermined number of bits; input interface means for feeding a portion of the image data, extracted from the image data in the memory means, which are to be contracted, as second series of second predetermined number of bits; DDA means for generating DDA bit pattern indicating valid bits in the second series according to a given contraction rate; correction means for detecting those second series which are fractional as a second series of second predetermined number of bits, and generating correction bit pattern indicating validity of last bits of the second series which are fractional as a second series of second predetermined number of bits; means for producing valid bit pattern indicating valid bits in the image data as the second series of second predetermined number of bits, in accordance with the DDA bit pattern and the correction bit pattern; and means for performing contraction of the extracted portion of the image data in accordance with the valid bit pattern.

Claim 11

The apparatus of claim 7, wherein the first predetermined number is an integer multiple of the second predetermined number, and wherein the correction means detects those second series which are fractional as a second series of second predetermined number of bits by first detecting leftmost and rightmost first series which are fractional as a first series of first predetermined number of bits from the left and right end bits of the extracted portion in the image data in the memory means, and then dividing the extracted portion into second series of second predetermined number of bits from top of the extracted portion.

Claim 12

The apparatus of claim 8, wherein the correction means comprises: means for deriving leftmost and rightmost first series which are fractional as a first series of first predetermined number of bits from the left and right end bits of the extracted portion in the image data in the memory means; means for calculating a sum of number of bits in the leftmost and the rightmost first series; and decoder means for generating the correction bit pattedrn indicating validity of last bits of the second series which are fractional as a second series of second predetermined number of bits, in accordance with the sum from the calculating means.

Claim 13

The apparatus of claim 7, wherein the correction means generates the correction bit pattern only when the image data are not fractional as a series of predetermined number of bits, and wherein the producing means produces the valid bit pattern in accordance with the DDA bit pattern only when the image data are not fractional as a series of predetermined number of bits.

Claim 14

The apparatus of claim 7, wherein the producing means comprises plurality of OR gates which output OR of the DDA bit pattern and the correction bit pattern as the valid bit pattern.

Claim 15

An image processing apparatus of parallel processing type using DDA method for processing image data, the apparatus comprising: DDA means for generating DDA bit patterns; means for calculating an extraction starting bit width and an extraction ending bit width indicating a portion of the image data to be extracted; and means for performing contraction of the portion of the image data in accordance with the DDA bit patterns, the extraction starting bit width, and the extraction ending bit width.

Claim 16

An image processing apparatus of parallel processing type using DDA method for processing image data, the apparatus comprising: DDA means for generating DDA bit patterns; means for calculating an extraction starting bit width and an extraction ending bit width indicating a portion of the image data to be extracted; and means for performing contraction of the portion of the image data in accordance with the DDA bit patterns, the extraction starting bit width, and the extraction ending bit width.

Claim 17

The apparatus of claim 12, wherein the performing means includes means for deriving bit patterns indicating presence of fractional image data, from the extraction starting bit width and the extraction ending bit width.

Claim 18

The apparatus of claim 13, wherein the derived bit patterns further indicate that a last bit of the fractional image data is valid.

Claim 19

The apparatus of claim 14, wherein the performing means further includes: OR gates to which the DDA bit patterns and the derived bit patterns are given; and NAND gates to which the iamge data and outputs of OR gates are given.