US4955075A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Battery saver circuit for a frequency synthesizer
Assignee: Motorola Solutions Inc
•
Filing: 1988-10-17
•
Granted: 1990-09-04
•
Expires: 2008-10-17
Abstract
Abstract A radio receiver (102) receives on a selected one of a plurality of channels, one of which is a control channel. A continuous signal is transmitted on the control channel. A frequency synthesizer (122) includes a voltage controlled oscillator (VCO 124) and a plurality of phase lock circuits (126), such as a phase detector (130), a reference oscillator (134), a programmable divider (128) and a loop filter (132). The input of the VCO can be switched between the phase lock circuits and an automatic frequency control circuit (AFC 114), which is connected to the radio receiver. When the radio receiver is receiving a quality control channel signal, the switch is positioned to select the AFC circuit and, consequently, the VCO is frequency locked to the control channel signal. Whenever the VCO is locked to the control channel signal, one or more of the phase lock circuits are deactivated, thereby reducing power consumption. When the radio receiver is tuned to a channel other than the control channel, the VCO is phase locked to the reference oscillator by activating the phase lock circuits and positioning the switch such that the VCO input is coupled to the phase lock circuits.
Inventors
- 👤 George C. Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:29
CPC Classifications
H; H04; H04W; H04W52/00; H04W52/02; H04W52/0209; H04W52/0261; H04W52/0274; H04W52/028; H04W52/0283; Y; Y02; Y02D; Y02D30/00; Y02D30/70
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
166 words
A battery saver circuit, comprising in combination: a controlled oscillator having a control input and producing an output signal; selectable frequency lock means for frequency locking said output signal to a control signal; selectable phase lock means for phase locking said output signal to a reference signal; control means, switchably coupled to the control input of said controlled oscillator, for selecting one of said frequency lock and phase lock means: said frequency lock means comprising: a comparator circuit, a first input of said comparator circuit being coupled to said phase lock means; a sample and hold circuit, the input of said sample and hold circuit being coupled to the output of said comparator circuit; and a summing circuit, a first input of said summing circuit being coupled to the output of said sample and hold circuit, a second input of said summing circuit being coupled to said control signal, and the output of said summing circuit being coupled to a second input of said comparator circuit.
Claim 2
Dependent Claim
166 words
A battery saver circuit, comprising in combination: a controlled oscillator having a control input and producing an output signal; selectable frequency lock means for frequency locking said output signal to a control signal; selectable phase lock means for phase locking said output signal to a reference signal; control means, switchably coupled to the control input of said controlled oscillator, for selecting one of said frequency lock and phase lock means: said frequency lock means comprising: a comparator circuit, a first input of said comparator circuit being coupled to said phase lock means; a sample and hold circuit, the input of said sample and hold circuit being coupled to the output of said comparator circuit; and a summing circuit, a first input of said summing circuit being coupled to the output of said sample and hold circuit, a second input of said summing circuit being coupled to said control signal, and the output of said summing circuit being coupled to a second input of said comparator circuit.
Claim 3
Dependent Claim
67 words
The battery saver circuit of claim 1, wherein said control means includes: a switch having first and second positions, an output of said phase lock means being coupled to an input of said frequency synthesizer when said switch is in said first position, and said output of said summing circuit being coupled to said input of said frequency synthesizer when said switch is in said second position.
Claim 4
Dependent Claim
68 words
The battery saver circuit of claim 1, wherein said control means includes: a switch having first and second positions, an output of said phase lock means being coupled to an input of said frequency synthesizer when said switch is in said first position, and an output of said frequency lock means being coupled to said input of said frequency synthesizer when said switch is in said second position.
Claim 5
Dependent Claim
243 words
A battery saver circuit for use in a communications system including a plurality of channels, one of said channels being a control channel, said control channel having a control channel signal, said battery saver circuit comprising in combination: a frequency synthesizer including a controlled oscillator having a control input and selectable phase lock means for phase locking said controlled oscillator to a reference signal; selectable automatic frequency control (AFC) means for frequency locking said controlled oscillator to said control channel signal; receiving means, coupled to said AFC means, for receiving signals on selected ones of said channels; and control means, switchably coupled to the control input of said controlled oscillator, for selecting said AFC means when said receiving means is receiving said control channel signal, and for disabling a portion of said phase lock means when said AFC means is selected, whereby the power consumption of said frequency synthesizer is reduced: said frequency lock means comprising: comparator means, a first input of said comparator means being coupled to said phase lock means: sample and hold means, the input of said sample and hold means being coupled to the output of said comparator means: summing means, a first input of said summing circuit means coupled to the output of said sample and hold means, a second input of said summing means being coupled to said control signal, and the output of said summing means being coupled to a second input of said comparator means.
Claim 6
Dependent Claim
243 words
A battery saver circuit for use in a communications system including a plurality of channels, one of said channels being a control channel, said control channel having a control channel signal, said battery saver circuit comprising in combination: a frequency synthesizer including a controlled oscillator having a control input and selectable phase lock means for phase locking said controlled oscillator to a reference signal; selectable automatic frequency control (AFC) means for frequency locking said controlled oscillator to said control channel signal; receiving means, coupled to said AFC means, for receiving signals on selected ones of said channels; and control means, switchably coupled to the control input of said controlled oscillator, for selecting said AFC means when said receiving means is receiving said control channel signal, and for disabling a portion of said phase lock means when said AFC means is selected, whereby the power consumption of said frequency synthesizer is reduced: said frequency lock means comprising: comparator means, a first input of said comparator means being coupled to said phase lock means: sample and hold means, the input of said sample and hold means being coupled to the output of said comparator means: summing means, a first input of said summing circuit means coupled to the output of said sample and hold means, a second input of said summing means being coupled to said control signal, and the output of said summing means being coupled to a second input of said comparator means.
Claim 7
Dependent Claim
60 words
The battery saver circuit of claim 4, wherein: said receiving means further includes signal quality means for measuring the quality of said control channel signal; and said control means includes means for selecting said phase lock means when said receiving means is receiving said control channel signal and the quality of said control channel signal is below a predetermined threshold.
Claim 8
Dependent Claim
67 words
The battery saver circuit of claim 5, wherein said control means includes: a switch having first and second positions, an output of said phase lock means being coupled to an input of said controlled oscillator when said switch is in said first position, and an output of said AFC means being coupled to said input of said controlled oscillator when said switch is in said second position.
Claim 9
Dependent Claim
67 words
The battery saver circuit of claim 6, wherein said control means includes: a switch having first and second positions, an output of said phase lock means being coupled to an input of said controlled oscillator when said switch is in said first position, and said output of said summing circuit being coupled to said input of said controlled oscillator when said switch is in said second position.
Claim 10
Dependent Claim
67 words
The battery saver circuit of claim 4, wherein said control means includes: a switch having first and second positions, an output of said phase lock means being coupled to an input of said controlled oscillator when said switch is in said first position, and an output of said AFC means being coupled to said input of said controlled oscillator when said switch is in said second position.
Claim 11
Dependent Claim
193 words
A battery saver circuit for a frequency synthesizer having controlled oscillator means having a control input; high and low power operating modes, comprising: frequency lock means for frequency locking a synthesizer output signal to a control signal; phase lock means for phase locking the synthesizer output signal to a reference signal; and selecting means connected to the control input of said controlled oscillator means for selecting the frequency lock means when the frequency synthesizer is operating in the low power operating mode, and for selecting the phase lock means, when the frequency synthesizer is operating in the high power operating mode; said frequency lock means comprising: comparator means, a first input of said comparator means being coupled to said phase lock means: sample and hold means, the input of said sample and hold means being coupled to the output of said comparator means: summing means, a first input of said summing means being coupled to the output of said sample and hold means, a second input of said summing means being coupled to said control signal, and the output of said summing means being coupled to a second input of said comparator means.
Claim 12
Dependent Claim
193 words
A battery saver circuit for a frequency synthesizer having controlled oscillator means having a control input; high and low power operating modes, comprising: frequency lock means for frequency locking a synthesizer output signal to a control signal; phase lock means for phase locking the synthesizer output signal to a reference signal; and selecting means connected to the control input of said controlled oscillator means for selecting the frequency lock means when the frequency synthesizer is operating in the low power operating mode, and for selecting the phase lock means, when the frequency synthesizer is operating in the high power operating mode; said frequency lock means comprising: comparator means, a first input of said comparator means being coupled to said phase lock means: sample and hold means, the input of said sample and hold means being coupled to the output of said comparator means: summing means, a first input of said summing means being coupled to the output of said sample and hold means, a second input of said summing means being coupled to said control signal, and the output of said summing means being coupled to a second input of said comparator means.
References Cited (Backward Citations)
US4349789A
Cited
US4365349A
Cited
US4521918A
Cited
US4651104A
Cited
US4721924A
Cited
US4596046A
Cited
US4817197A
Cited
US4703520A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-03 | 1994-03-05 | 1994-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-03 | 1998-03-05 | 1998-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-03 | 2002-03-05 | 2002-09-04 | $7700.00 | Window Closed / Lapsed |