US4955054A
Expired / Lapsed
US
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Integrated telecommunication system with improved digital voice response
Assignee: VICORP HOLDING Co LLC
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Filing: 1988-10-05
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Granted: 1990-09-04
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Expires: 2008-10-05
Abstract
Abstract An integrated telecommunication system for multiple telephone line response and processing having a plurality of interface circuits, each of which is adapted to control the physical connection to a plurality of telephone line channels, control communication on a group of telephone line channels connected thereto. Each interface circuit includes a high speed interface microprocessor and a first data storage associated therewith. A first bus system interconnects the plurality of interface processor circuits to signal processor circuits. Each signal processor module includes a cross-point switch and a high speed digital signal microprocessor for analyzing the incoming signals and compressing the data therein, a second data storage associated therewith, and one or more of a plurality of telecommunication function circuits controlled thereby. A multi-bus system connects each of the plurality of interface processors to each of the plurality of signal processor circuits and to a main system control processor and a third data storage. The high speed processing requirements of each group of telephone lines is performed by the respective interface control processor and a digital signal microprocessor and main system control processor selectively controls the storage of data in the first, second and third data storages and intercommunication functions between the plurality of interface processor circuits and the plurality of signal processor circuits and the function circuits controlled thereby.
Inventors
- 👤 Ferrell W. Boyd, Jr.
- 👤 Michael Murdock
- 👤 Michael McCormack
- 👤 Paul Darbee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:14
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0407; H04M; H04M3/00; H04M3/42; H04M3/50
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
258 words
An integrated telecommunication system for multiple telephone line response and processing comprising: a plurality of interface processor circuits, each of which is adapted to control the physical connection to a plurality of telephone line channels and control communication on a group of said telephone line channels connected thereto. each said interface circuit including a high speed interface control microprocessor and a first data storage associated therewith, a plurality of signal processor circuit means, each said signal processor circuit means including crosspoint switch means for receiving multiple line mutiple channel inputs and producing corresponding multiple line multiple channel outputs, and a high speed digital signal microprocessor for analyzing the incoming signals and compressing the data therein, and a second data storage associated therewith, for controlling one or more telecommunication function circuits, a main system control microprocessor, a first bus system for connecting said plurality of interface processor circuits to said plurality of signal processor circuit means, and a second bus system for connecting each of said plurality of interface processor circuits to each of said plurality of signal processor circuit means and to said main system control microprocessor, whereby the high speed processing requirements of each said group of telephone lines is performed by said interface processor circuits and said digital signal microprocessor and said main system control microprocessor controls the storage of data in said first and second data storages and intercommunication functions between said plurality of interface processor circuits and said plurality of signal processor circuit means and said one or more telecommunication function circuits controlled thereby.
Claim 2
Dependent Claim
258 words
An integrated telecommunication system for multiple telephone line response and processing comprising: a plurality of interface processor circuits, each of which is adapted to control the physical connection to a plurality of telephone line channels and control communication on a group of said telephone line channels connected thereto. each said interface circuit including a high speed interface control microprocessor and a first data storage associated therewith, a plurality of signal processor circuit means, each said signal processor circuit means including crosspoint switch means for receiving multiple line mutiple channel inputs and producing corresponding multiple line multiple channel outputs, and a high speed digital signal microprocessor for analyzing the incoming signals and compressing the data therein, and a second data storage associated therewith, for controlling one or more telecommunication function circuits, a main system control microprocessor, a first bus system for connecting said plurality of interface processor circuits to said plurality of signal processor circuit means, and a second bus system for connecting each of said plurality of interface processor circuits to each of said plurality of signal processor circuit means and to said main system control microprocessor, whereby the high speed processing requirements of each said group of telephone lines is performed by said interface processor circuits and said digital signal microprocessor and said main system control microprocessor controls the storage of data in said first and second data storages and intercommunication functions between said plurality of interface processor circuits and said plurality of signal processor circuit means and said one or more telecommunication function circuits controlled thereby.
Claim 3
Dependent Claim
72 words
The integrated telecommunication system defined in claim 1 wherein each of said plurality of interface processor circuits includes a telephone line interface circuit chip, a call progress interface chip and a facility data link chip and means connecting said interface circuit chip, call progress interface chip and said facility data link chip to said high speed interface control microprocessor, and means to supply a program to said high speed interface control microprocessor.
Claim 4
Dependent Claim
28 words
The integrated telecommunication system defined in claim 1 including a permanent data storage means and means connecting said permanent data storage means to said main system control microprocessor.
Claim 5
Dependent Claim
250 words
An integrated telecommunication system for multiple telephone line response and processing comprising: a plurality of interface processor circuits, each of which is adapted to control the physical connection to a plurality of telephone line channels, and control communication on a group of said telephone line channels connected thereto, and each interface processor circuit including a high speed interface control microprocessor, respectively, a plurality of signal processor circuit means, each said signal processor circuit means including crosspoint switch means for receiving multiple line multiple channel inputs and producing corresponding multiple line multiple channel outputs, and a high speed digital signal microprocessor for analyzing the incoming signals and compressing the data therein, and one or more telecommunication function circuit means controlled thereby, a main system control microprocessor, and data storage means connected thereto, a first bus system for connecting said plurality of interface processor circuits to said plurality of signal processor circuit means, and a second bus system for connecting each of said plurality of interface processor circuits to each of said plurality of signal processor circuit means and to said main system control microprocessor, whereby the high speed processing requirements of said group of telephone line channels is performed by said interface processor circuits and said digital signal microprocessor and said main system control microprocessor controls the storage of data in said data storage means and intercommunication functions between said plurality of interface processor circuits and said plurality of signal processor circuit means and said telecommunication function circuit means controlled thereby.
Claim 6
Dependent Claim
250 words
An integrated telecommunication system for multiple telephone line response and processing comprising: a plurality of interface processor circuits, each of which is adapted to control the physical connection to a plurality of telephone line channels, and control communication on a group of said telephone line channels connected thereto, and each interface processor circuit including a high speed interface control microprocessor, respectively, a plurality of signal processor circuit means, each said signal processor circuit means including crosspoint switch means for receiving multiple line multiple channel inputs and producing corresponding multiple line multiple channel outputs, and a high speed digital signal microprocessor for analyzing the incoming signals and compressing the data therein, and one or more telecommunication function circuit means controlled thereby, a main system control microprocessor, and data storage means connected thereto, a first bus system for connecting said plurality of interface processor circuits to said plurality of signal processor circuit means, and a second bus system for connecting each of said plurality of interface processor circuits to each of said plurality of signal processor circuit means and to said main system control microprocessor, whereby the high speed processing requirements of said group of telephone line channels is performed by said interface processor circuits and said digital signal microprocessor and said main system control microprocessor controls the storage of data in said data storage means and intercommunication functions between said plurality of interface processor circuits and said plurality of signal processor circuit means and said telecommunication function circuit means controlled thereby.
Claim 7
Dependent Claim
72 words
The integrated telecommunication system defined in claim 4 wherein each of said plurality of interface processor circuits includes a telephone line interface circuit chip, a call progress interface chip and a facility data link chip and means connecting said interface circuit chip, call progress interface chip and said facility data link chip to said high speed interface control microprocessor, and means to supply a program to said high speed interface control microprocessor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-03 | 1994-03-05 | 1994-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-03 | 1998-03-05 | 1998-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-03 | 2002-03-05 | 2002-09-04 | $7700.00 | Window Closed / Lapsed |