US4954978A
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Priority order decomposing apparatus
Assignee: Mitsubishi Electric Corp
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Filing: 1988-05-25
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Granted: 1990-09-04
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Expires: 2008-05-25
Abstract
Abstract A priority order decomposing apparatus converting binary data of a plurality of bits into data wherein "1"s other than "1" of the bit whose priority order is the highest are removed, a circuit for checking whether or not "1" exists is installed for each group of bits taken as a unit of converting process. When "1" exists, this is transmitted directly to the low-order-bit side to immediately set the lower-order bits to "0". This permits the operating speed to be made faster.
Inventors
- 👤 Hideyuki Terane
- 👤 Shinichi Nakagawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:23
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/74
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
184 words
A priority order decomposing apparatus for processing input data having a plurality of logic circuits comprising: m number of first inclusive-or circuits respectively receiving one bit of a m-bit word as a first input, m number of exclusive-or circuits respectively receiving outputs of said first inclusive-or circuits, and a second inclusive-or circuit receiving m number of said first input and a one-bit second input as inputs thereof, wherein the first inclusive-or circuit and the exclusive-or circuit of the highest-order bit receive the second input as the other input, and the other first inclusive-or circuits and exclusive-or circuits receive the output of the first inclusive-or circuit of the high-order-bit side as the other input thereof, the logic circuits being connected in a cascade manner with the output of the second inclusive-or circuit received as the second input of the logic circuit of the low-order-bit side and the first input of the logic circuit of the highest-order-bit side set to a predetermined potential, and the input data is received as the first input, and the output of said exclusive-or circuit is transmitted as a processed output.
Claim 2
Dependent Claim
184 words
A priority order decomposing apparatus for processing input data having a plurality of logic circuits comprising: m number of first inclusive-or circuits respectively receiving one bit of a m-bit word as a first input, m number of exclusive-or circuits respectively receiving outputs of said first inclusive-or circuits, and a second inclusive-or circuit receiving m number of said first input and a one-bit second input as inputs thereof, wherein the first inclusive-or circuit and the exclusive-or circuit of the highest-order bit receive the second input as the other input, and the other first inclusive-or circuits and exclusive-or circuits receive the output of the first inclusive-or circuit of the high-order-bit side as the other input thereof, the logic circuits being connected in a cascade manner with the output of the second inclusive-or circuit received as the second input of the logic circuit of the low-order-bit side and the first input of the logic circuit of the highest-order-bit side set to a predetermined potential, and the input data is received as the first input, and the output of said exclusive-or circuit is transmitted as a processed output.
Claim 3
Dependent Claim
100 words
A logic circuit comprising: m number of first inclusive-or circuits respectively receiving one bit of a m-bit word as a first input, m number of exclusive-or circuits respectively receiving outputs of said first inclusive-or circuits; a second inclusive-or circuit receiving m number of said first input and a one-bit second input as inputs thereof; the first inclusive-or circuit and the exclusive-or circuit of the highest-order bit receive a second input as the other input; and the other first inclusive-or circuits and exclusive-or circuits take the output of the first inclusive-or circuit of the high-order-bit side as the other input thereof.
Claim 4
Dependent Claim
100 words
A logic circuit comprising: m number of first inclusive-or circuits respectively receiving one bit of a m-bit word as a first input, m number of exclusive-or circuits respectively receiving outputs of said first inclusive-or circuits; a second inclusive-or circuit receiving m number of said first input and a one-bit second input as inputs thereof; the first inclusive-or circuit and the exclusive-or circuit of the highest-order bit receive a second input as the other input; and the other first inclusive-or circuits and exclusive-or circuits take the output of the first inclusive-or circuit of the high-order-bit side as the other input thereof.
Claim 5
Dependent Claim
205 words
A priority order decomposing apparatus for processing input data having a plurality of logic circuits comprising: m number of first inclusive-or circuits respectively receiving one bit of a m-bit word as a first input, m number of one-input inversion type logic product circuits respectively receiving outputs of said first inclusive-or circuits on respective non-inversion input terminals, and a second inclusive-or circuit receiving m number of said first input and a one-bit second input as inputs thereof, wherein the first inclusive-or circuit and the one-input inversion type logic product circuit of the highest-order bit receive the second input as the other input thereof, and the other first inclusive-or circuits and one-input inversion type logic product circuits receive the output of the first inclusive-or circuit of the high-order-bit side as the other input thereof, the logic circuits being connected in a cascade manner with the output of the second inclusive-or circuit received as the second input of the logic circuit of the low-order-bit side and the first input of the logic circuit of the highest-order-bit-side set to a predetermined potential, and the input data is received as the first input, and the output of said one-input inversion type logic product circuit is transmitted as a processed output.
Claim 6
Dependent Claim
205 words
A priority order decomposing apparatus for processing input data having a plurality of logic circuits comprising: m number of first inclusive-or circuits respectively receiving one bit of a m-bit word as a first input, m number of one-input inversion type logic product circuits respectively receiving outputs of said first inclusive-or circuits on respective non-inversion input terminals, and a second inclusive-or circuit receiving m number of said first input and a one-bit second input as inputs thereof, wherein the first inclusive-or circuit and the one-input inversion type logic product circuit of the highest-order bit receive the second input as the other input thereof, and the other first inclusive-or circuits and one-input inversion type logic product circuits receive the output of the first inclusive-or circuit of the high-order-bit side as the other input thereof, the logic circuits being connected in a cascade manner with the output of the second inclusive-or circuit received as the second input of the logic circuit of the low-order-bit side and the first input of the logic circuit of the highest-order-bit-side set to a predetermined potential, and the input data is received as the first input, and the output of said one-input inversion type logic product circuit is transmitted as a processed output.
Claim 7
Dependent Claim
120 words
A logic circuit comprising: m number of first inclusive-or circuits respectively receiving one bit of a m-bit word as a first input, m number of one-input inversion type logic product circuits respectively receiving outputs of said first inclusive-or circuits on respective non-inversion input terminals thereof, and a second inclusive-or circuit receiving m number of said first input and a one-bit second input as inputs thereof, wherein the first inclusive-or circuit and the one-input inversion type logic product circuit of the highest-order bit receive the second input as the other input, and the other first inclusive-or circuits and one-input inversion type logic product circuits receive the output of the first inclusive-or circuit of the high-order-bit side as the other input therof.
Claim 8
Dependent Claim
120 words
A logic circuit comprising: m number of first inclusive-or circuits respectively receiving one bit of a m-bit word as a first input, m number of one-input inversion type logic product circuits respectively receiving outputs of said first inclusive-or circuits on respective non-inversion input terminals thereof, and a second inclusive-or circuit receiving m number of said first input and a one-bit second input as inputs thereof, wherein the first inclusive-or circuit and the one-input inversion type logic product circuit of the highest-order bit receive the second input as the other input, and the other first inclusive-or circuits and one-input inversion type logic product circuits receive the output of the first inclusive-or circuit of the high-order-bit side as the other input therof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-03 | 1994-03-05 | 1994-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-03 | 1998-03-05 | 1998-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-03 | 2002-03-05 | 2002-09-04 | $7700.00 | Window Closed / Lapsed |