US4953119A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiplier circuit with selectively interconnected pipelined multipliers for selectively multiplication of fixed and floating point numbers
Assignee: Raytheon Co
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Filing: 1989-01-27
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Granted: 1990-08-28
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Expires: 2009-01-27
Abstract
Abstract A multiplier which processes 32 bit operands to provide two 16 bit by 16 bit fixed point products or one 32 bit floating point product during each clock pulse. Two 16 bit by 16 bit fixed point products or one 32 bit floating point product are initiated on every clock pulse and results of the multiplication process are available after a fixed pipeline delay on a continuous basis. The fixed and floating point pipeline operations may also be interleaved. The 32 bit input operands are selected from three external sources or from the last output product. A modified Booth algorithm is implemented employing dual parallel processing paths which are employed to separately produce the 16 bit by 16 bit fixed point products or are combined to produce the 32 bit floating point product. Exponent computations are performed in parallel in the floating point computational mode.
Inventors
- 👤 Kenneth J. Wong
- 👤 Steven P. Davies
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 23:15
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/533; G06F7/5334; G06F7/5336; G06F7/5338; G06F7/4806; G06F7/4812; G06F7/483; G06F7/487; G06F7/4876; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3812; G06F2207/382; G06F2207/386; G06F2207/3884
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
271 words
A multiplier circuit for selectively performing real and complex fixed point, and floating-point arithmetic multiplications on a plurality of input words having a predetermined data word length, said multiplier circuit comprising: input logic means for receiving a plurality of input data words having a predetermined data word length for providing first and second output words comprising least and most significant portions of the input data words; multiplier means coupled to the input logic means for receiving the first and second output words, and comprising first and second selectively interconnected parallel pipelined multiplier paths configured to implement a modified Booth algorithm for processing the least significant words and most significant words of the first and second output words, respectively, when performing floating-point multiplications, and for processing respective ones of the plurality of input words along the respective multiplier paths when performing fixed-point multiplications; the first and second multiplier paths each comprising first and second serially connected multipliers having a first pipeline register connected therebetween, and further comprising a second pipeline register connected to an output of the second pipeline register; and first and second adders respectively coupled to an output of the second multipliers of each path, the adder of the first multiplier path having an output selectively couplable to an input of the adder of the second multiplier path to provide a carry input thereto; wherein the multiplier means performs floating-point multiplication when the first and second parallel pipelined multiplier paths and the first and second adders are interconnected, and performs fixed-point multiplication when the first and second parallel pipelined multiplier paths and the first and second adders are selectively disconnected.
Claim 2
Dependent Claim
271 words
A multiplier circuit for selectively performing real and complex fixed point, and floating-point arithmetic multiplications on a plurality of input words having a predetermined data word length, said multiplier circuit comprising: input logic means for receiving a plurality of input data words having a predetermined data word length for providing first and second output words comprising least and most significant portions of the input data words; multiplier means coupled to the input logic means for receiving the first and second output words, and comprising first and second selectively interconnected parallel pipelined multiplier paths configured to implement a modified Booth algorithm for processing the least significant words and most significant words of the first and second output words, respectively, when performing floating-point multiplications, and for processing respective ones of the plurality of input words along the respective multiplier paths when performing fixed-point multiplications; the first and second multiplier paths each comprising first and second serially connected multipliers having a first pipeline register connected therebetween, and further comprising a second pipeline register connected to an output of the second pipeline register; and first and second adders respectively coupled to an output of the second multipliers of each path, the adder of the first multiplier path having an output selectively couplable to an input of the adder of the second multiplier path to provide a carry input thereto; wherein the multiplier means performs floating-point multiplication when the first and second parallel pipelined multiplier paths and the first and second adders are interconnected, and performs fixed-point multiplication when the first and second parallel pipelined multiplier paths and the first and second adders are selectively disconnected.
Claim 3
Dependent Claim
94 words
The multiplier of claim 1 wherein said multiplier circuit means further comprises: first and second serially coupled multipliers disposed in each path, the multipliers of each respective path having recoding logic coupled the input logic means for receiving respective most significant words therefrom, and having the first multiplier of each respective path coupled to the input logic means for receiving respective least significant words therefrom; and an adder coupled to the first and second multipliers of each path for combining partial product outputs of the multipliers to form an output product of the multipliers.
Claim 4
Dependent Claim
36 words
The multiplier of claim 1 wherein said multiplier circuit means further comprises: exponent processing means coupled in parallel with the multiplier means for processing exponential values associated with floating point multiplications performed by the multiplier means.
Claim 5
Dependent Claim
295 words
A multiplier circuit for selectively performing real and complex fixed-point, and floating-point arithmetic multiplications on a plurality of input words having a predetermined data word length, said multiplier circuit comprising: input logic means for receiving a plurality of input data words having a predetermined data word length, and for providing first and second output words comprising least and most significant portions of the input data words; multiplier means coupled to the input logic means for receiving the first and second output words, and comprising first and second selectively interconnected parallel pipelined multiplier paths for implementing a modified Booth algorithm, for processing the least significant words and most significant words of the first and second output words, respectively; the first and second multiplier paths each including first and second serially connected multipliers having a first pipeline register connected therebetween, and a second pipeline register connected to an output of the second multiplier, each path further including an adder coupled to an output of the second multiplier, the adder of the first multiplier path having an output selectively coupled to an input of the adder of the second multiplier path to provide a carry input thereto; the multiplier means further comprising first and second selectively coupled data paths that are selectively interconnected to respective first and second multipliers, and a selectively coupled data register path selectively interconnecting the first pipeline register of the first multiplier path to the second multiplier of the second multiplier path; wherein the multiplier circuit performs fixed-point multiplication when the first multiplier path, second multiplier path, and data register paths and the first and second adders are coupled together, and performs floating-point multiplication when the first multiplier path, second multiplier path, and data register paths and the first and second adders are decoupled.
Claim 6
Dependent Claim
295 words
A multiplier circuit for selectively performing real and complex fixed-point, and floating-point arithmetic multiplications on a plurality of input words having a predetermined data word length, said multiplier circuit comprising: input logic means for receiving a plurality of input data words having a predetermined data word length, and for providing first and second output words comprising least and most significant portions of the input data words; multiplier means coupled to the input logic means for receiving the first and second output words, and comprising first and second selectively interconnected parallel pipelined multiplier paths for implementing a modified Booth algorithm, for processing the least significant words and most significant words of the first and second output words, respectively; the first and second multiplier paths each including first and second serially connected multipliers having a first pipeline register connected therebetween, and a second pipeline register connected to an output of the second multiplier, each path further including an adder coupled to an output of the second multiplier, the adder of the first multiplier path having an output selectively coupled to an input of the adder of the second multiplier path to provide a carry input thereto; the multiplier means further comprising first and second selectively coupled data paths that are selectively interconnected to respective first and second multipliers, and a selectively coupled data register path selectively interconnecting the first pipeline register of the first multiplier path to the second multiplier of the second multiplier path; wherein the multiplier circuit performs fixed-point multiplication when the first multiplier path, second multiplier path, and data register paths and the first and second adders are coupled together, and performs floating-point multiplication when the first multiplier path, second multiplier path, and data register paths and the first and second adders are decoupled.
Claim 7
Dependent Claim
264 words
A multiplier circuit for selectively performing real and complex fixed-point, and floating-point arithmetic multiplications on a plurality of input words having a predetermined data word length, said multiplier circuit comprising: input logic means for receiving a plurality of input data words having a predetermined data word length, for providing first and second output words; multiplier means coupled to the input logic means for receiving the first and second output words, and comprising first and second selectively interconnected parallel pipelined multiplier paths for implementing a modified Booth algorithm; the first and second multiplier paths each including first and second serially connected multipliers having a first pipeline register connected therebetween, and a second pipeline register connected to an output of the second multiplier, each path further including an adder coupled to an output of the second multiplier, the adder of the first multiplier path having an output selectively couplable to an input of the adder of the second multiplier path to provide a carry input thereto; the multiplier means further comprising first and second selectively couplable data paths that are selectively interconnected to respective first and second multipliers, and a selectively couplable data register path selectively interconnecting the first multiplier of the first multiplier path to the second multiplier of the second multiplier path; wherein the multiplier circuit performs fixed-point multiplication when the first multiplier path, second multiplier path, and data register paths and the first and second adders are coupled together, and performs floating-point multiplication when the first multiplier path, second multiplier path, and data register paths and the first and second adders are decoupled.
Claim 8
Dependent Claim
264 words
A multiplier circuit for selectively performing real and complex fixed-point, and floating-point arithmetic multiplications on a plurality of input words having a predetermined data word length, said multiplier circuit comprising: input logic means for receiving a plurality of input data words having a predetermined data word length, for providing first and second output words; multiplier means coupled to the input logic means for receiving the first and second output words, and comprising first and second selectively interconnected parallel pipelined multiplier paths for implementing a modified Booth algorithm; the first and second multiplier paths each including first and second serially connected multipliers having a first pipeline register connected therebetween, and a second pipeline register connected to an output of the second multiplier, each path further including an adder coupled to an output of the second multiplier, the adder of the first multiplier path having an output selectively couplable to an input of the adder of the second multiplier path to provide a carry input thereto; the multiplier means further comprising first and second selectively couplable data paths that are selectively interconnected to respective first and second multipliers, and a selectively couplable data register path selectively interconnecting the first multiplier of the first multiplier path to the second multiplier of the second multiplier path; wherein the multiplier circuit performs fixed-point multiplication when the first multiplier path, second multiplier path, and data register paths and the first and second adders are coupled together, and performs floating-point multiplication when the first multiplier path, second multiplier path, and data register paths and the first and second adders are decoupled.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-27 | 1994-02-26 | 1994-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-27 | 1998-02-26 | 1998-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-27 | 2002-02-26 | 2002-08-28 | $7700.00 | Window Closed / Lapsed |