Cache memory address modifier for dynamic alteration of cache block fetch sequence

Claim 2

A cache memory address modifier for dynamic alteration of a cache block fetch sequence from a main memory which includes a plurality of memory modules, comprising: word address receiving means for receiving a first memory word address of a first desired word of a storage block comprising a plurality of words to be fetched from main memory, the first memory word address identifying a storage location in a particular memory module of said plurality of memory modules of said main memory from which the first desired word is to be fetched; testing means coupled to said word address receiving means and to the main memory, for testing the particular memory module associated with the memory word address and for determining whether the particular memory module is free to process a data return in response to receipt of the first memory word address, or whether said particular memory module is inhibited and thereby issuing a memory inhibit signal; and dynamic address alteration means coupled to said testing means and responsive to said memory inhibit signal for generating a second memory word address of a second desired word of the storage block when the testing means indicates that the particular memory module is inhibited, the second memory word address identifying a second memory word of the storage block, said dynamic address alteration means further comprising means for selecting by priority a free memory module of said plurality of memory modules other than said particular memory module storing the second desired word which has not yet been fetched.

Claim 3

A cache memory address modifier for dynamic alteration of a cache block fetch sequence from main memory as defined in claim 1, wherein the means for selecting by priority includes a priority encoder.

Claim 4

A cache memory address modifier for dynamic alteration of a cache block fetch sequence from main memory as defined in claim 1, wherein the testing means includes a plurality of OR gates and wherein said dynamic address alteration means includes means for generating a fetch priority signal indicative of whether said first desired word has previously been fetched, each OR gate of said plurality being connected to receive said fetch priority signal and the memory inhibit signal indicative as to whether the particular memory module of the main memory is inhibited or is free.

Claim 5

A cache memory address modifier for dynamic alteration of a cache block fetch sequence from a main memory as defined in claim 3, wherein the dynamic address alteration means further includes a multiplexer controlled by an output of one of the OR gates so that when the particular memory module is free and the first desired word has not been fetched the word address of said first desired word is output to the main memory for subsequently attempting to retrieve said first desired word and said means for selecting by priority generates a signal indicative of the highest priority unfetched word of said storage block in said free memory module other than said particular memory module so that when the first desired word has been previously fetched or the particular memory module is inhibited, said signal is received from said means for selecting by priority to fetch the highest priority unfetched word residing in said free memory module.

Claim 6

A cache memory address modifier for dynamic alteration of a cache block fetch sequence from a main memory which includes a plurality of memory modules, comprising: word address receiving means for receiving a first memory word address of a first desired word of a storage block comprising a plurality of words to be fetched from main memory, the first memory word address identifying a storage location in a particular memory module of said plurality of memory modules of said main memory from which the first desired word is to be fetched; testing means coupled to said word address receiving means and to the main memory, for testing the particular memory module associated with the first memory word address and for determining whether the particular memory module is free to process a data return in response to receipt of the memory word address, or whether said particular memory module is inhibited and thereby issuing a memory inhibit signal; dynamic address alteration means coupled to said testing means and responsive to said memory inhibit signal for generating a second memory word address of a second desired word of the storage block when the testing means indicates that the particular memory module is inhibited, the second memory word address identifying a second memory word of the storage block; and wherein the testing means includes a plurality of OR gates and wherein said dynamic address alteration means includes means for generating a fetch priority signal indicative of whether said first desired word has previously been fetched, each OR gate of said plurality being connected to receive said fetch priority signal and the memory inhibit signal indicative as to whether the particular memory module of the main memory is inhibited or is free.

Claim 7

A cache memory address modifier for dynamic alteration of a cache block fetch sequence from a main memory which includes a plurality of memory modules, comprising: word address receiving means for receiving a first memory word address of a first desired word of a storage block comprising a plurality of words to be fetched from main memory, the first memory word address identifying a storage location in a particular memory module of said plurality of memory modules of said main memory from which the first desired word is to be fetched; testing means coupled to said word address receiving means and to the main memory, for testing the particular memory module associated with the first memory word address and for determining whether the particular memory module is free to process a data return in response to receipt of the memory word address, or whether said particular memory module is inhibited and thereby issuing a memory inhibit signal; dynamic address alteration means coupled to said testing means and responsive to said memory inhibit signal for generating a second memory word address of a second desired word of the storage block when the testing means indicates that the particular memory module is inhibited, the second memory word address identifying a second memory word of the storage block; and wherein the testing means includes a plurality of OR gates and wherein said dynamic address alteration means includes means for generating a fetch priority signal indicative of whether said first desired word has previously been fetched, each OR gate of said plurality being connected to receive said fetch priority signal and the memory inhibit signal indicative as to whether the particular memory module of the main memory is inhibited or is free.

Claim 8

A cache memory address modifier for dynamic alteration of a cache block fetch sequence from a main memory as defined in claim 5, wherein the dynamic address alteration means further includes a multiplexer controlled by an output of one of the OR gates so that when the particular memory module is free and the first desired word has not been fetched the word address of said first desired word is output to the main memory for subsequently attempting to retrieve said first desired word and means for selecting by priority for generating a signal indicating the highest priority unfetched word of said storage block in a free memory module other than said particular memory module so that when the first desired word has been previously fetched or the particular memory module is inhibited, said signal is received from said means for selecting by priority the highest priority unfetched word residing in said free memory module.