Semiconductor device

Claim 2

A semiconductor device comprising: a semiconductor element; and a wiring portion including an intersection of a first and a second lead, wherein said intersection comprises a semiconductor layer and a insulating layer which are laminated between said first and second leads, and wherein an average potential of said second lead joined to said insulating layer relative to an average potential of said first lead joined to said semiconductor layer has a direction such that a supply of carriers from said first lead to said semiconductor layer is prevented.

Claim 3

A semiconductor device according to claim 1, wherein said semiconductor layer includes an i-layer and an n + -layer, and wherein said first lead has a higher average potential than that of said second lead.

Claim 4

A semiconductor device according to claim 1, wherein said first lead forms a Schottky barrier against said semiconductor layer.

Claim 5

A semiconductor device according to claim 1, wherein said semiconductor layer is made of an amorphous silicon hydride.

Claim 6

A semiconductor device according to claim 1, wherein said semiconductor element comprises a photoelectric conversion element.

Claim 7

A semiconductor device according to claim 1, wherein said semiconductor device comprises a contact type sensor.

Claim 8

A semiconductor device according to claim 1, wherein said semiconductor device comprises a liquid crystal display.

Claim 9

A semiconductor device according to claim 1, wherein said semiconductor device comprises an integrated circuit.

Claim 10

A semiconductor device comprising: a substrate; a plurality of semiconductor elements disposed on said substrate, each of said semiconductor elements including a respective photoelectric conversion element having a semiconductor region; and a wiring portion disposed on said substrate and further comprising: a plurality of first leads each electrically connected to a respective one of said semiconductor elements, a plurality of second leads each electrically connected to at least one of said plurality of first lead, a plurality of third leads, provided among said second leads, and an insulating region comprising a lamination of a semiconductor layer and an insulating layer, and disposed between said first and said third leads at intersections thereof, wherein said third leads are maintained at a predetermined potential to prevent a supply of carriers to said semiconductor layer.

Claim 11

A semiconductor device comprising: a substrate; a plurality of semiconductor elements disposed on said substrate, each of said semiconductor elements including a respective photoelectric conversion element having a semiconductor region; and a wiring portion disposed on said substrate and further comprising: a plurality of first leads each electrically connected to a respective one of said semiconductor elements, a plurality of second leads each electrically connected to at least one of said plurality of first lead, a plurality of third leads, provided among said second leads, and an insulating region comprising a lamination of a semiconductor layer and an insulating layer, and disposed between said first and said third leads at intersections thereof, wherein said third leads are maintained at a predetermined potential to prevent a supply of carriers to said semiconductor layer.

Claim 12

A semiconductor device according to claim 9, wherein each of said intersections includes a corresponding one of said first leads, said semiconductor layer being provided on that first lead through said insulating layer, and a corresponding one of said second or third leads provided on the semiconductor layer through an n + -layer, and wherein an average potential of individual said first lead is lower than that of said second or third lead.

Claim 13

A semiconductor device according to claim 9, wherein each of said intersections includes a corresponding one of said first leads, the semiconductor layer being provided on that first lead through said insulating layer, and a corresponding one of said second or third leads provided on the semiconductor layer through a p + -layer, and wherein an average potential of said first lead is higher than that of said second or third lead.

Claim 14

A semiconductor device according to claim 9, wherein each of said intersections includes a corresponding one of said second or said third leads, said semiconductor layer being provided on said second of said third lead through said insulating layer, and a corresponding one of said first leads provided on said semiconductor layer through an n + -layer, and wherein an average potential of said first is higher than that of said second or third lead.

Claim 15

A semiconductor layer according to claim 9, wherein each of said intersections includes a corresponding one of said second or said third leads, said semiconductor layer provided on said second or said third lead through said insulating layer, and a corresponding one of said first leads provided on said semiconductor layer through a p + -layer, and wherein an average potential of said first lead is lower than that of said second or third lead.

Claim 16

A semiconductor layer according to claim 9, wherein said semiconductor layer is made of amorphous silicon hydride.

Claim 17

A semiconductor device according to claim 9, wherein said voltage source applies a direct current voltage.

Claim 18

A semiconductor device according to claim 9, wherein said voltage source applies a pulse voltage.

Claim 19

A semiconductor device according to claim 9, wherein the predetermined potential is obtained by applying a direct current voltage.

Claim 20

A semiconductor device according to claim 9, wherein the predetermined potential is obtained by applying a pulse voltage.

Claim 23

An apparatus according to claim 19, wherein said apparatus comprises a facsimile machine.

Claim 24

A semiconductor device comprising: a substrate; a plurality of photoelectric conversion elements disposed on said substrate, each of said conversion elements including a semiconductor layer for photoelectric conversion and a respective individual electrode electrically connected to said semiconductor layer; a matrix of leads electrically connected to said photoelectric conversion elements; and a plurality of leads provided among said matrix of leads and held at a predetermined potential, wherein said respective individual electrodes and said plurality of leads have corresponding intersections, each of said intersections having said semiconductor layer and an insulating layer between a corresponding one of said individual electrodes and a corresponding one of said leads, wherein said individual electrode is maintained at an average potential such that a supply of carriers to said semiconductor layer is prevented, and wherein said semiconductor layer is provided on said individual electrode through said insulating layer and said lead is provided on said semiconductor layer through a p + -layer, an average potential of said individual electrode being higher than that of said corresponding lead.

Claim 25

A semiconductor device comprising: a substrate; a plurality of photoelectric conversion elements disposed on said substrate, each of said conversion elements including a semiconductor layer for photoelectric conversion and a respective individual electrode electrically connected to said semiconductor layer; a matrix of leads electrically connected to said photoelectric conversion elements; and a plurality of leads provided among said matrix of leads and held at a predetermined potential, wherein said respective individual electrodes and said plurality of leads have corresponding intersections, each of said intersections having said semiconductor layer and an insulating layer between a corresponding one of said individual electrodes and a corresponding one of said leads, wherein said individual electrode is maintained at an average potential such that a supply of carriers to said semiconductor layer is prevented, and wherein said semiconductor layer is provided on said individual electrode through said insulating layer and said lead is provided on said semiconductor layer through a p + -layer, an average potential of said individual electrode being higher than that of said corresponding lead.

Claim 26

A semiconductor device comprising: a substrate; a plurality of photoelectric conversion elements disposed on said substrate, each of said conversion elements including a semiconductor layer for photoelectric conversion and a respective individual electrode electrically connected to said semiconductor layer; a matrix of leads electrically connected to said photoelectric conversion elements; and a plurality of leads provided among said matrix of leads and held at a predetermined potential, wherein said respective individual electrodes and said plurality of leads have corresponding intersections, each of said intersections having said semiconductor layer and an insulating layer between a corresponding one of such individual electrodes and a corresponding one of said leads, wherein said individual electrode is maintained at an average potential such that a supply of carriers to said semiconductor layer is prevented, and wherein said corresponding individual electrode is provided on said semiconductor layer through a p + -layer, wherein an the average potential of each individual electrode is lower than that of corresponding said lead.

Claim 27

A semiconductor device comprising: a substrate; a plurality of photoelectric conversion elements disposed on said substrate, each of said conversion elements including a semiconductor layer for photoelectric conversion and a respective individual electrode electrically connected to said semiconductor layer; a matrix of leads electrically connected to said photoelectric conversion elements; and a plurality of leads provided among said matrix of leads and held at a predetermined potential, wherein said respective individual electrodes and said plurality of leads have corresponding intersections, each of said intersections having said semiconductor layer and an insulating layer between a corresponding one of such individual electrodes and a corresponding one of said leads, wherein said individual electrode is maintained at an average potential such that a supply of carriers to said semiconductor layer is prevented, and wherein said corresponding individual electrode is provided on said semiconductor layer through a p + -layer, wherein an the average potential of each individual electrode is lower than that of corresponding said lead.