Vital processing system including a vital power controller with forgiveness feature

Claim 2

A vital power controller for verifying the proper operation of a vital processing system and for providing vital power to the system outputs only when the system is functioning correctly comprising: (1) a microprocessor adapted to receive odd and even checkword sets, and including means for converting the checkword sets so as to produce a vital drive signal at an output of said microprocessor; (2) a passive detector for receiving said vital drive signal at its input and providing a low power DC voltage at its output; (3) a DC-to-DC converter for receiving said low power DC voltage at its input and providing vital power at its output; (4) said means for converting said checkword sets including a feedback shift register, a read-only memory having odd and even tables stored therein, whereby a valid checkword set enables the vital power controller to generate said vital power for a time limited by the number of entries in said tables; and (5) means for discriminating between noise events occurring at a relatively low rate compared with the rate encountered with hardware failures, said means for discriminating including a plurality of forgiveness buffers connected to said feedback shift register, each of said buffers being operative to initialize said feedback shift register for generating said vital drive signal for a period equivalent to that for a valid checkword set.

Claim 3

A device as defined in claim 1, in which each of said forgiveness buffers is configured as a polynomial divider.

Claim 4

A vital power controller as defined in claim 1, in which said read-only memory in said means for converting contains a forgiveness table for operating said vital power controller during cycles of forgiveness such that these cycles cannot be confused with the normal odd or even checkword cycles.

Claim 5

A device as defined in claim 3, further comprising means for destroying the contents of each forgiveness buffer when such buffer has been used in the cycle of forgiveness process.

Claim 6

A device as defined in claim 1, in which each of said forgiveness buffers is first initialized to a value taken from a table of cycle of forgiveness initialization values.

Claim 7

A device as defined in claim 5, including means for feeding the final state of said feedback shift register into a forgiveness buffer each time a valid odd or even checkword set is processed, thereby to change each buffer state so that after a fixed number of valid checkword cycles, the forgiveness buffer will contain the value which can be used to provide a cycle of forgiveness.

Claim 8

A device as defined in claim 1, in which each of said cycle of forgiveness buffers is first initialized to a value taken from a table of cycle of forgiveness initialization values.

Claim 9

A device as defined in claim 7, including means for feeding the final state of said feedback shift register into a forgiveness buffer each time a valid odd or even checkword set is processed, thereby to change each buffer state, so that after a fixed number of valid checkword cycles, the forgiveness buffer will contain the values which can be used to provide a cycle of forgiveness.

Claim 10

A vital power controller, a vital power controller for verifying the proper operation of a vital processing system and for providing vital power to the system outputs only when the system is functioning correctly comprising: (1) a microprocessor adapted to receive odd and even checkword sets, and including means for converting the checkword sets so as to produce a vital drive signal at an output of said microprocessor; (2) a passive detector for receiving said vital drive signal at its input and providing a low power DC voltage at its output; (3) a DC-to-DC converter for receiving said low power DC voltage at its input and providing vital power at its output; the improvement comprising an arrangement in which said microprocessor includes: (a) a feedback shift register as part of said means for converting; a read-only memory having odd and even tables stored therein, whereby a valid checkword set enables the vital power controller to generate said vital power for a time limited by the number of entries in said tables; and (b) means for discriminating between noise events occurring at a relatively low rate compared with the rate encountered with hardware failures, said means for discriminating including a plurality of forgiveness buffers connected to said feedback shift register, said buffers being selectively operative to initialize said feedback shift register for generating said vital drive signal for a period equivalent to that for a valid checkword set.

Claim 11

A vital power controller, a vital power controller for verifying the proper operation of a vital processing system and for providing vital power to the system outputs only when the system is functioning correctly comprising: (1) a microprocessor adapted to receive odd and even checkword sets, and including means for converting the checkword sets so as to produce a vital drive signal at an output of said microprocessor; (2) a passive detector for receiving said vital drive signal at its input and providing a low power DC voltage at its output; (3) a DC-to-DC converter for receiving said low power DC voltage at its input and providing vital power at its output; the improvement comprising an arrangement in which said microprocessor includes: (a) a feedback shift register as part of said means for converting; a read-only memory having odd and even tables stored therein, whereby a valid checkword set enables the vital power controller to generate said vital power for a time limited by the number of entries in said tables; and (b) means for discriminating between noise events occurring at a relatively low rate compared with the rate encountered with hardware failures, said means for discriminating including a plurality of forgiveness buffers connected to said feedback shift register, said buffers being selectively operative to initialize said feedback shift register for generating said vital drive signal for a period equivalent to that for a valid checkword set.

Claim 12

A device as defined in claim 9, in which each of said cycle of forgiveness buffers is configured as a polynomial divider.

Claim 13

A vital power controller as defined in claim 9, in which said read-only memory in said means for converting contains a forgiveness table for operating said vital power controller during cycles of forgiveness such that these cycles cannot be confused with the normal odd or even checkword cycles.

Claim 14

A device as defined in claim 11, further comprising means for destroying the contents of each forgiveness buffer when such buffer has been used in the cycle of forgiveness process.