US4949238A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for detecting memory protection violation
Assignee: Toshiba Corp
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Filing: 1988-02-11
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Granted: 1990-08-14
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Expires: 2008-02-11
Abstract
Abstract To detect a memory protection violation at high speed in a data processor for executing microinstructions, plural memory protection information of a descriptor of a new segment program are simultaneously discriminated true or false on the basis of current privilege level and branch condition information of a memory protection branch microinstruction. If discriminated true, the succeeding microinstruction is selected. If false, the current microinstruction is branched to a designated branch address included in the branch microinstruction. The apparatus comprises, an attribute information register for storing plural memory protection information of a new decriptor; a current privilege level register; a privilege level comparator; a microinstruction register for storing a memory protection branch microinstruction including plural branch condition information and a branch address; a memory protection violation detector having AND gates, inverters, and an OR gate; and a read address selector having an adder, etc.
Inventors
- 👤 Shigeo Kamiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 01:04
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1458; G06F12/1491
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
251 words
An apparatus for detecting a memory protection violation in a data processor for executing microinstructions under control of microprograms, which comprises: (a) attribute information register means for storing a plurality of memory protection information of a descriptor of a program whenever any one of an instruction segment, a stack segment or a non-stack segment is changed, said memory protection information including data of description validity, descriptor privilege level, descriptor type, code/data discrimination and write-enable; (b) current privilege level register means for storing a current privilege level of a program now being executed; (c) comparator means for comparing a descriptor privilege level of said memory protection information stored in said attribute information register means with said current privilege level stored in said current privilege level register means; (d) microinstruction register means for storing a memory protection branch microinstruction including branch condition information and a branch address; (e) means for simultaneously discriminating whether said plurality of memory protection information stored in said attribute information register means are correct or not on the basis of the comparison result of said comparator means and said branch condition information stored in said microinstruction register means and for generating a memory protection violation detection signal when not correct; (f) means for selecting a succeeding microinstruction execution in response to the absence of said memory protection violation detection signal and a microinstruction branch operation in accordance with said branch address stored in said microinstruction register means in response to the presence of said memory protection violation detection signal.
Claim 2
Independent Claim
251 words
An apparatus for detecting a memory protection violation in a data processor for executing microinstructions under control of microprograms, which comprises: (a) attribute information register means for storing a plurality of memory protection information of a descriptor of a program whenever any one of an instruction segment, a stack segment or a non-stack segment is changed, said memory protection information including data of description validity, descriptor privilege level, descriptor type, code/data discrimination and write-enable; (b) current privilege level register means for storing a current privilege level of a program now being executed; (c) comparator means for comparing a descriptor privilege level of said memory protection information stored in said attribute information register means with said current privilege level stored in said current privilege level register means; (d) microinstruction register means for storing a memory protection branch microinstruction including branch condition information and a branch address; (e) means for simultaneously discriminating whether said plurality of memory protection information stored in said attribute information register means are correct or not on the basis of the comparison result of said comparator means and said branch condition information stored in said microinstruction register means and for generating a memory protection violation detection signal when not correct; (f) means for selecting a succeeding microinstruction execution in response to the absence of said memory protection violation detection signal and a microinstruction branch operation in accordance with said branch address stored in said microinstruction register means in response to the presence of said memory protection violation detection signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-13 | 1994-02-12 | 1994-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-13 | 1998-02-12 | 1998-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-13 | 2002-02-12 | 2002-08-14 | $7700.00 | Window Closed / Lapsed |