Process control patch generator

Claim 3

The patch generating system of claim 1 wherein the memory means stores data for only a small number of pixels in a small number of lines of the patch.

Claim 4

The patch generating system of claim 1 wherein the memory means stores data for only two lines of the patch.

Claim 5

The patch generating system of claim 1 wherein the memory means stores data for only eight pixels in each of the first two lines of the patch.

Claim 6

The patch generating system of claim 1 wherein the pixel data is stored in one-bit binary form with each pixel being either completely on or off.

Claim 7

The patch generating system of claim 1 wherein the outputting means supplies data for complete lines to be written on the charge-retaining member.

Claim 8

The patch generating system of claim 6 wherein the stored patch data is only supplied by the outputting means for a small portion of the lines.

Claim 9

The patch generating system of claim 7 wherein the outputting means supplies data which indicates blank pixels for the portions of the lines not containing the patch data.

Claim 10

The patch generating system of claim 6 wherein the outputting means also includes: means for counting the number of pixels represented by the line output data; means for outputting blank pixel data for each line containing the patch until said counting means reaches a first address; means for outputting the patch data for each line after the first address has been counted and before a second address has been counted; and means for outputting blank pixel data for each line to the completion of the line after the second address has been counted.

Claim 11

The patch generating system of claim 9 wherein the blank pixel data for the lines is generated by maintaining a predetermined output state from the outputting means when the stored patch pixel data is not being outputted.

Claim 14

The method for generating a process control patch of claim 11 wherein the pixel data is in binary form for specifying a pixel either as completely printed or blank.

Claim 15

The method for generating a process control patch of claim 11 including the step of transferring, from another system, the pixel data to be stored.

Claim 16

The method for generating a process control patch of claim 13 wherein the pixel data is stored in at least one register of the system.

Claim 17

The method for generating a process control patch of claim 14 wherein the density of the patch is determined by the density of the pixel data stored.

Claim 18

Circuitry for generating a process control patch on a charge-retaining member of a hardcopy output device having means for developing said patch, said circuitry comprising: means for writing pixel data onto the charge-retaining member in response to lines of pixel data; means for counting pixels and lines; means for comparing location addresses of the patch with the pixel and line counts; first and second registers loaded with pixel data for the patch; and controllable gate circuitry for controlling the flow of pixel data from the registers to the writing means; said comparing means activating the controllable gate for flow of data from the registers when the pixel counter is between start and stop addresses for the patch, and deactivating the controllable gate when the pixel counter is not between start and stop addresses to cause the writing means to only obtain data indicating blank pixels when the gate is deactivated.

Claim 19

Circuitry for generating a process control patch on a charge-retaining member of a hardcopy output device having means for developing said patch, said circuitry comprising: means for writing pixel data onto the charge-retaining member in response to lines of pixel data; means for counting pixels and lines; means for comparing location addresses of the patch with the pixel and line counts; first and second registers loaded with pixel data for the patch; and controllable gate circuitry for controlling the flow of pixel data from the registers to the writing means; said comparing means activating the controllable gate for flow of data from the registers when the pixel counter is between start and stop addresses for the patch, and deactivating the controllable gate when the pixel counter is not between start and stop addresses to cause the writing means to only obtain data indicating blank pixels when the gate is deactivated.

Claim 20

The patch generating circuitry of claim 16 wherein the data is stored in pixel form in two registers from data downloaded from another system.

Claim 21

The patch generating circuitry of claim 17 wherein the data in the two registers is stored in binary form with both binary states existing in the stored data.

Claim 22

The patch generating circuitry of claim 17 wherein the circuitry also includes a line counter which alternates the flow of data between the two registers.