Method and circuit for filtering signals representative of a picture

Claim 2

Process for two-dimensional filtering of data signals representative of pixels of a two-dimensional picture by convolution by a convolution kernel having MxN coefficient, M and N being predetermined integers, comprising the steps of: (a) scanning a picture to be processed column per column in successive horizontal bands each having a height equal to an entire fraction of the height of the picture, whereby a representation of the picture as pixels distributed in rows and columns is obtained, each band having a common predetermined number of rows, (b) fractionating said picture into mutually adjacent blocks of pixels each having M pixels in each of N mutually adjacent columns, and (c) computing the transforms of all pixels in a same block in MxN computing cycles by: computing in parallel, during a same computing cycle, all partial convolution products of a single one of the MxN coefficients of the convolution kernel and of the data of all of those pixels which provide a partial product necessary for computation of the transforms of all pixels of the block, in a window of the picture containing the block, the cycle being repeated for each coefficient in turn; and summing all the partial products obtained at each cycle, for each pixel of the respective block, and (d) repeating step (c) on each of the remaining blocks.

Claim 3

Process according to claim 1, wherein, during step (a), the picture is scanned in bands having M pixels per column.

Claim 4

Circuit for two-dimensional convolution filtering with a convolution kernel having MxN coefficients, M and N being integers greater than 1, of data representative of pixels of a two-dimensional picture, comprising: scanning means for scanning a picture to be processed, column per column, in successive horizontal bands each having a height equal to an entire fraction of the picture, whereby a representation of the picture as pixels distributed in rows and columns is obtained, all bands having a same predetermined number of rows, a matrix array of MxN processors distributed in M rows of N processors, first means for distributing one convolution coefficient of the convolution kernel at a time to all the processors during a same computing cycle and for replacing the coefficient with another coefficient when passing from one cycle to the next, until MxN successive cycles have been carried out, and second means for applying to each processor, during each of MxN successive cycles, data representative of a set of pixels of a window of the picture which includes the block, the pixels of said set having an offset with respect to the position of the coefficient distributed during the cycle which remains unchanged for each cycle, said array of processors being arranged for computing MxN partial convolution products of one coefficient of the kernel during a same cycle and for summing, progressively during the MxN successive cycles, the partial convolution products for all the coefficients of the kernel and for storing the value resulting from the summation.

Claim 5

Circuit for two-dimensional convolution filtering with a convolution kernel having MxN coefficients, M and N being integers greater than 1, of data representative of pixels of a two-dimensional picture, comprising: scanning means for scanning a picture to be processed, column per column, in successive horizontal bands each having a height equal to an entire fraction of the picture, whereby a representation of the picture as pixels distributed in rows and columns is obtained, all bands having a same predetermined number of rows, a matrix array of MxN processors distributed in M rows of N processors, first means for distributing one convolution coefficient of the convolution kernel at a time to all the processors during a same computing cycle and for replacing the coefficient with another coefficient when passing from one cycle to the next, until MxN successive cycles have been carried out, and second means for applying to each processor, during each of MxN successive cycles, data representative of a set of pixels of a window of the picture which includes the block, the pixels of said set having an offset with respect to the position of the coefficient distributed during the cycle which remains unchanged for each cycle, said array of processors being arranged for computing MxN partial convolution products of one coefficient of the kernel during a same cycle and for summing, progressively during the MxN successive cycles, the partial convolution products for all the coefficients of the kernel and for storing the value resulting from the summation.

Claim 6

Circuit according to claim 3, wherein the second means are arranged to simultaneously shift all data representing pixels of the picture through the array along such a path that each of said processors has summed all partial products necessary for computation of a predetermined one of said transforms on the respective block at the end of MxN cycles.

Claim 7

Circuit according to claim 4, wherein each of said processors comprises a circuit for computing a transform of one pixel and an input register connected to receive data representative of different pixels having different positions with respect to the pixel being transformed and to deliver the appropriate one of said pixels to an input of the circuit for computing the transform.

Claim 8

Circuit according to claim 5, wherein each of said processors further comprises an output register for selection between the output of said transform computing circuit and the output of the input register.

Claim 9

Circuit according to claim 5, wherein said input register of said processor has inputs connected to receive data respectively from the processors placed above, under,and at the right of said one processor in the array.

Claim 10

Circuit according to claim 5, wherein the tranform computing circuit comprises a multiplier for computing one partial product and accumulator means receiving the output of said multiplier.

Claim 11

Circuit according to claim 8, wherein the second means further comprise a general register connected to the input of said array of processors and having two inputs, one of said inputs being connected to directly receive pixel-representing data corresponding to the block to be processed while the other input receives pixel-representing data through a delay line providing a time delay corresponding to the scanning duration of a band of blocks.