Yoked, orthogonally distributed equal reactance amplifier

Claim 2

A Field Effect Transistor device comprising: one or more field effect transistor stages formed in a semiconductor monolith; each stage of said stages comprising a source, a drain, and a gate; said source and said gate of said each stage constituting the input portion of said each stage; said drain and said gate of said each stage constituting the output portion of said each stage; the geometry of said device, and the forming of said device in said semiconductor monolith, being effective to cause said input portion and said output portion of said each stage to be mirror images of one another; whereby said geometry and said forming of said device in said monolith is effective to cause the phase velocity of wave propagation in said input and said output stages of said each stage to be substantially identical, whereby to eliminate phase cancellation between said input portion and said output portion of said each stage.

Claim 3

The device of claim 1, wherein each said each stage of said one or more stages comprises: a unitary layer of doped semiconductor material, said unitary layer having a first region and a second region, said first and said second regions being more heavily doped than the remainder of said layer by a preselected amount; said first region of said each stage being effective as said source of said each stage; said second region being effective as said drain of said each stage; said remainder being effective as said channel of said each stage.

Claim 4

The device of claim 1, wherein said one or more stages is a plurality of stages sequentially yoked together, each said source and each said drain of adjacent stages of said plurality of stages being unitary and common to both of said adjacent stages, and wherein: said monolith comprises a unitary layer of doped semiconductor material, said unitary layer comprising said source, said drain, and said channel of said each stage; said channel of said each stage having a first region and a second region, said first and said second regions being more heavily doped than the remainder of said layer by a preselected amount; said first region of said each stage being effective as said source; said second region of said each stage being effective as said drain; said remainder of said each stage being effective as said channel; said first and second regions being effective to limit the magnitude of the potential difference within said first and said second regions respectively therein form exceeding a magnitude of about that corresponding to the maximum carrier equilibrium drift velocity in said semiconductor material; said semiconductor is n-doped gallium arsenide; said monolith is formed generally linearly symmetric about three orthogonal dimensions, a first dimension of said three dimensions being disposed in the direction of charge flow across said channel of said each stage, a second dimension of said three dimensions being disposed in the direction of wave propagation in said device; said layer being disposed generally in the plain formed by said first dimension and said second dimension; said first and said second region of said each stage being generally linear and extending along said second dimension; said gate of said each stage comprising a metal microstrip extending linearly along said second dimension; said source and said drain of said each stage comprising a metal microstrip overlaying said heavily doped region of said source and said drain; said monolith comprising a substrate of semi-insulating gallium arsenide disposed abuttingly adjacent said layer opposite said gate.

Claim 5

A travelling wave amplifier comprising: one or more field effect transistor stages formed in a semiconductor monolith; each stage of said one or more stages comprising a source, a drain, and a gate, said each stage being in a common gate configuration, said source and said gate of said each stage constituting the input waveguide of said each stage, said drain and said gate constituting the output waveguide of said each stage; and wherein said input waveguide and said output waveguide of said each stage are adapted to be impedance matched.

Claim 6

A travelling wave amplifier comprising: one or more field effect transistor stages formed in a semiconductor monolith; each stage of said one or more stages comprising a source, a drain, and a gate, said each stage being in a common gate configuration, said source and said gate of said each stage constituting the input waveguide of said each stage, said drain and said gate constituting the output waveguide of said each stage; and wherein said input waveguide and said output waveguide of said each stage are adapted to be impedance matched.

Claim 7

The amplifier of claim 4, wherein said input waveguide and said output waveguide are adapted to be impedance matched by said input and output waveguides being formed as mirror images of one another.

Claim 8

The amplifier of claim 5, wherein said one or more stages is a plurality of stages sequentially yoked together, each source and each drain of adjacent stages of said plurality of stages being unitary and common to both of said adjacent stages.

Claim 9

The amplifier of claim 6, wherein, for at least two adjacent stages, the unitary source and drain shared by said at least two adjacent stages is a portion of said semiconductor monolith, said portion of said semiconductor monolith having high doping with respect to the channels of both of said two adjacent stages, said high doping being of a sufficient magnitude to permit said portion of said semiconductor monolith to constitute a microstripline without external biasing or metalization of said portion.

Claim 10

The amplifier of claim 7, wherein said amplifier comprises means for limiting charge carrier velocity between said source and said drain of said each stage to at or below the maximum carrier drift velocity of the material constituting said channel.

Claim 11

The amplifier of claim 4, wherein said one or more stages is a plurality of stages sequentially yoked together, each source and each drain of adjacent stages of said plurality of stages being unitary and common to both of said adjacent stages.

Claim 12

The amplifier of claim 4, wherein, for at least two adjacent stages, the unitary source and drain shared by said at least two adjacent stages is a portion of said semiconductor monolith, said portion of said semiconductor monolith having high doping with respect to the channels of both of said two adjacent stages, said high doping being of a sufficient magnitude to permit said portion of said semiconductor monolith to constitute a microstripline without external biasing or metalization of said portion.

Claim 13

The amplifier of claim 4, wherein said amplifier comprises means for limiting charge carrier velocity between said source and said drain of said each stage to or below the maximum carrier drift velocity of the material constituting said channel.

Claim 14

The amplifier of claim 4, wherein said input waveguide and said output waveguide of said each stage are adapted to be impedance matched for traveling waves of wavelength smaller than about one millimeter.