US4945509A
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US
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Dual look ahead mask generator
Assignee: International Business Machines Corp
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Filing: 1988-03-14
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Granted: 1990-07-31
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Expires: 2008-03-14
Abstract
Abstract A mask generator for generating a mask having logical signals of a given level between positions indicated by beginning and ending addresses. Two decoders select respective binary signal lines indicating the starting and ending positions. The mask generator is composed of two mask generators operating on the higher and lower order binary signal lines respectively and which ripple from the ends of the mask towards the middle. Preferably, each of the dual mask generators has look-ahead carry capability.
Inventors
- 👤 Stephen B. Barrett
- 👤 John Bula
- 👤 Alvar A. Dean
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:16
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/764; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30018; G06F9/30036; G06F9/30038
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
266 words
A mask generator responsive to a starting address and an ending address for generating a mask word having a plurality of mask bits of a first logical level and a plurality of mask bits at a second logical level, with said plurality of mask bits of said first logical level beginning and ending at start and end positions in said mask word defined by said beginning and ending addresses, respectively, said mask generator comprising: decoder means for decoding said beginning and ending addresses and for providing a plurality of start outputs corresponding to said start address and a plurality of end outputs corresponding to said ending address; first ripple circuit means responsive to at least portions of each of said start and end outputs for generating a first ripple portion output including a plurality of bits forming a first portion of said mask word, said first ripple circuit, when said starting address indicates a start position within said first portion of said mask word, generating a first logical level signal propagating from said start position in said mask word towards a higher order bit position thereof; and second ripple circuit means responsive to at least portions of each of said start and end outputs for generating a second ripple circuit output including a plurality of bits forming a second portion of said mask word, said second ripple circuit, when said ending address indicates an end position in said second portion of said mask word, generating a first logical level signal propagating from said end position in said mask word towards a lower order bit position thereof.
Claim 2
Dependent Claim
266 words
A mask generator responsive to a starting address and an ending address for generating a mask word having a plurality of mask bits of a first logical level and a plurality of mask bits at a second logical level, with said plurality of mask bits of said first logical level beginning and ending at start and end positions in said mask word defined by said beginning and ending addresses, respectively, said mask generator comprising: decoder means for decoding said beginning and ending addresses and for providing a plurality of start outputs corresponding to said start address and a plurality of end outputs corresponding to said ending address; first ripple circuit means responsive to at least portions of each of said start and end outputs for generating a first ripple portion output including a plurality of bits forming a first portion of said mask word, said first ripple circuit, when said starting address indicates a start position within said first portion of said mask word, generating a first logical level signal propagating from said start position in said mask word towards a higher order bit position thereof; and second ripple circuit means responsive to at least portions of each of said start and end outputs for generating a second ripple circuit output including a plurality of bits forming a second portion of said mask word, said second ripple circuit, when said ending address indicates an end position in said second portion of said mask word, generating a first logical level signal propagating from said end position in said mask word towards a lower order bit position thereof.
Claim 3
Dependent Claim
24 words
A mask generator as recited in claim 1, wherein each of said ripple circuit means comprises a plurality of ripple circuits connected in series.
Claim 4
Dependent Claim
20 words
A mask generator as recited in claim 1, wherein said first and second ripple circuit means comprise look-ahead carry circuits.
Claim 5
Dependent Claim
27 words
A mask generator as recited in claim 1, wherein said first and second ripple circuits are responsive to mutually exclusive portions of said start and end outputs.
Claim 6
Dependent Claim
205 words
A mask generator for generating a mask word having a plurality of bits including at least one field of a first logical level extending from a start position to an end position, said mask generator comprising: a plurality of binary starting signal lines carrying respective binary starting signals, a selected one of which indicates said start position; a plurality of binary ending signal lines carrying respective binary ending signals, a selected one of which indicates said end position; a first ripple circuit means connected to lower order ones of said binary starting and ending signal lines for forming a lower order portion of said mask word and rippling said first logical level from said start position of said mask word to a higher order position of said mask word when said start position is within said lower order portion of said mask word; and a second ripple circuit means connected to higher order ones of said binary starting and ending signal lines for forming a higher order portion of said mask word and rippling said first logical level from said end position to a lower order position of said mask word when said end position is within said higher order portion of said mask word.
Claim 7
Dependent Claim
205 words
A mask generator for generating a mask word having a plurality of bits including at least one field of a first logical level extending from a start position to an end position, said mask generator comprising: a plurality of binary starting signal lines carrying respective binary starting signals, a selected one of which indicates said start position; a plurality of binary ending signal lines carrying respective binary ending signals, a selected one of which indicates said end position; a first ripple circuit means connected to lower order ones of said binary starting and ending signal lines for forming a lower order portion of said mask word and rippling said first logical level from said start position of said mask word to a higher order position of said mask word when said start position is within said lower order portion of said mask word; and a second ripple circuit means connected to higher order ones of said binary starting and ending signal lines for forming a higher order portion of said mask word and rippling said first logical level from said end position to a lower order position of said mask word when said end position is within said higher order portion of said mask word.
Claim 8
Dependent Claim
74 words
A mask generator as recited in claim 5, wherein each of said first and second ripple means comprises: a plurality of second-level ripple circuits each connected to a different set of binary starting and ending signal lines; and at least one look-ahead carry circuit connected to a same set of said binary starting and ending signals as one of said second-level ripple circuits and providing an input to another of said second-level ripple circuits.
Claim 9
Dependent Claim
63 words
A mask generator as recited in claim 6, wherein each of said second-level ripple circuits comprises a plurality of OR gates each receiving a respective one of said binary starting signal lines and a respective one of said binary ending line signal lines, said binary starting and ending line signals connected to said OR gate differing by one position corresponding to said mask.
Claim 10
Dependent Claim
33 words
A mask generator as recited in claim 7, wherein each of said second-level ripple circuits further comprises an exclusive-OR gate receiving an output of said OR gate in said each second-level ripple circuit.
Claim 11
Dependent Claim
69 words
A mask generator as recited in claim 8, wherein said look-ahead carry circuit comprises a first OR circuit receiving a plurality of binary starting signal lines, a second OR circuit receiving a plurality of binary ending signal lines, and logic means for combining outputs of said first and second OR circuits to produce an output having a value corresponding to an output of one of said second-level ripple circuits.
Claim 12
Dependent Claim
31 words
A mask generator as recited in claim 9, further comprising two decoders receiving binary encoded starting and ending signals and selecting respective ones of said binary starting and ending signal lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-30 | 1994-01-29 | 1994-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-30 | 1998-01-29 | 1998-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-30 | 2002-01-29 | 2002-07-31 | $7700.00 | Window Closed / Lapsed |