US4945497A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for translating rectilinear information into scan line information for display by a computer system
Assignee: Sun Microsystems Inc
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Filing: 1988-12-20
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Granted: 1990-07-31
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Expires: 2008-12-20
Abstract
Abstract A circuit which computes the scan position of any pixel on the display as the sum of the number of scan lines multiplied by the number of pixels per scan line plus the number of pixels on the scan line to the particular position using an adder for a changing portion of the computation and an incrementer for a constant portion of the computation and combining the two of these to produce a result which accomplishes in a relatively economic fashion what would normally require an inordinate number of gates to obtain a variety of screen resolutions which are not simply powers of two multiples of one another.
Inventors
- 👤 Chris Malachowsky
- 👤 Curtis Priem
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:51
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/391; G09G5/393
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
226 words
An apparatus for translating addresses corresponding to rectilinear coordinates of a plurality of scan line masks generated by a mask generator into addresses for a linear memory interface for the rapid display of an image on an output display, comprising: an adder coupled to said linear memory interface for providing a plurality of resolutions upon which said scan line masks may be displayed on said output display; first circuit means connected to said adder for providing a first input thereto, said first circuit means being coupled to said mask generator for receiving a Y rectilinear value therefrom, said first circuit means being further provided with an input indicative of a desired resolution for said output display; second circuit means coupled to said adder for providing a second input thereto, said second circuit means being coupled to said mask generator for receiving a Y rectilinear value therefrom, said second circuit being further provided with an input indicative of a desired resolution for said output display; and third circuit means coupled to said mask generator for providing a third input to said adder, said third circuit means being coupled to said mask generator for receiving a Y rectilinear value and the highest bit value of a X rectilinear value therefrom, said third input being provided with the value of the first ten bits of a X rectilinear coordinate.
Claim 2
Independent Claim
226 words
An apparatus for translating addresses corresponding to rectilinear coordinates of a plurality of scan line masks generated by a mask generator into addresses for a linear memory interface for the rapid display of an image on an output display, comprising: an adder coupled to said linear memory interface for providing a plurality of resolutions upon which said scan line masks may be displayed on said output display; first circuit means connected to said adder for providing a first input thereto, said first circuit means being coupled to said mask generator for receiving a Y rectilinear value therefrom, said first circuit means being further provided with an input indicative of a desired resolution for said output display; second circuit means coupled to said adder for providing a second input thereto, said second circuit means being coupled to said mask generator for receiving a Y rectilinear value therefrom, said second circuit being further provided with an input indicative of a desired resolution for said output display; and third circuit means coupled to said mask generator for providing a third input to said adder, said third circuit means being coupled to said mask generator for receiving a Y rectilinear value and the highest bit value of a X rectilinear value therefrom, said third input being provided with the value of the first ten bits of a X rectilinear coordinate.
Claim 3
Dependent Claim
21 words
An apparatus as defined in claim 1, wherein said resolutions are other than a power of two multiple of said resolution.
Claim 4
Dependent Claim
32 words
An apparatus as defined in claim 1, wherein said first circuit means is a multiplexer, said multiplexer providing a multiple of said Y rectilinear value as said first input to said adder.
Claim 5
Dependent Claim
32 words
An apparatus as defined in claim 1, wherein said second circuit means is a multiplexer, said multiplexer providing a multiple of said Y rectilinear value as said second input to said adder.
Claim 6
Dependent Claim
34 words
An apparatus as defined in claim 1, wherein said third circuit means is an incrementer, said incrementer providing a multiple of said Y rectilinear value as part of said third input to said adder.
Claim 7
Dependent Claim
24 words
An apparatus as defined in claim 1, wherein said Y rectilinear value comprises the Y rectilinear coordinate of said scan line describing said image.
Claim 8
Dependent Claim
24 words
An apparatus as defined in claim 1, wherein said X rectilinear value comprises the left most x-coordinate of said scan line describing said image.
Claim 9
Dependent Claim
25 words
The third input as defined in claim 1 further comprises a sum of said X rectilinear value and a multiple of said Y rectilinear value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-30 | 1994-01-29 | 1994-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-30 | 1998-01-29 | 1998-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-30 | 2002-01-29 | 2002-07-31 | $7700.00 | Window Closed / Lapsed |