US4942559A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Counter/timer circuit for a microcontroller
Assignee: Siemens AG
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Filing: 1989-07-07
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Granted: 1990-07-17
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Expires: 2009-07-07
Abstract
Abstract A counter/timer circuit for a microcontroller includes a central register and two auxiliary registers each having transfer outputs and counting inputs. Bistable output storage elements are each connected to a respective one of the transfer outputs. Interrupt request flags are also each connected to a respective one of the transfer outputs. Start/stop elements are each connected to a respective one of the counting inputs. Input control blocks are each connected to a respective one of the start/stop elements. First reload, capture and compare units are connected between one of the auxiliary registers and the central register, and second reload, capture and compare units are connected between the other of the auxiliary registers and the central register.
Inventors
- 👤 Rod Fleck
- 👤 Mark Poret
- 👤 Karl-Heinz Mattheis
- 👤 Javier Magana
- 👤 Christoph Meinhold
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:12
CPC Classifications
G; G04; G04G; G04G99/00; G04G99/006; G04G15/00; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/042; G05B19/0423
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
112 words
Counter/timer circuit for a microcontroller, comprising a central register and two auxiliary registers each having transfer outputs and counting inputs, bistable output storage elements each being connected to a respective one of said transfer outputs, interrupt request flags each being connected to a respective one of said transfer outputs, start/stop elements each being connected to a respective one of said counting inputs, input control blocks each being connected to a respective one of said start/stop elements, first reload, capture and compare units connected between one of said auxiliary registers and said central register, and second reload, capture and compare units connected between the other of said auxiliary registers and said central register.
Claim 2
Dependent Claim
112 words
Counter/timer circuit for a microcontroller, comprising a central register and two auxiliary registers each having transfer outputs and counting inputs, bistable output storage elements each being connected to a respective one of said transfer outputs, interrupt request flags each being connected to a respective one of said transfer outputs, start/stop elements each being connected to a respective one of said counting inputs, input control blocks each being connected to a respective one of said start/stop elements, first reload, capture and compare units connected between one of said auxiliary registers and said central register, and second reload, capture and compare units connected between the other of said auxiliary registers and said central register.
Claim 3
Dependent Claim
15 words
Counter/timer circuit according to claim 1, wherein said registers are programmable independently of one another.
Claim 4
Dependent Claim
24 words
Counter/timer circuit according to claim 1, wherein each of said input control blocks includes an input control circuit and upward/downward counting direction control means.
Claim 5
Dependent Claim
23 words
Counter/timer circuit according to claim 3, wherein at least one of said input control circuits receives a system clock rate of the microcontroller.
Claim 6
Dependent Claim
26 words
Counter/timer circuit according to claim 3, including input pins of the microcontroller connected to said input control circuit and to said upward/downward counting direction control means.
Claim 7
Dependent Claim
51 words
Counter/timer circuit according to claim 1, wherein said input control blocks have inputs, said bistable output storage elements have outputs, and said output of said bistable output storage element connected to said central register is connected to said input of each of said input control blocks connected to said auxiliary registers.
Claim 8
Dependent Claim
35 words
Counter/timer circuit according to claim 1, wherein said bistable output storage elements have inputs, and said transfer output of said central register is connected to said inputs of all of said bistable output storage elements.
Claim 9
Dependent Claim
61 words
Counter/timer circuit according to claim 1, wherein said input control block connected to one of said auxiliary registers is connected directly to said interrupt request flag connected to said one auxiliary register, and said input control block connected to the other of said auxiliary registers is connected directly to said interrupt request flag connected to the other of said auxiliary registers.
Claim 10
Dependent Claim
61 words
Counter/timer circuit according to claim 1, wherein said input control block connected to one of said auxiliary registers is connected to said reload and capture units connected to said one auxiliary register, and said input control block connected to the other of said auxiliary registers is connected to said reload and capture units connected to the other of said auxiliary registers.
References Cited (Backward Citations)
US4376995A
Cited
US4879733A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-16 | 1994-01-15 | 1994-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-16 | 1998-01-15 | 1998-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-16 | 2002-01-15 | 2002-07-17 | $7700.00 | Window Closed / Lapsed |