Compound semiconductor field-effect transistor

Claim 2

A field effect transistor comprising: a source and a drain; a channel region between said source and said drain; a gate formed on said channel region; and two planar-doped layers, each of said planar-doped layers having two-dimensionally doped impurities, said planar-doped layers being located within said channel region, being in contact with both said source and said drain, and being separated by an interval which is equal to or smaller than about 70 Å.

Claim 3

A field effect transistor as claimed in claim 1, wherein said channel region is formed in a compound semiconductor layer.

Claim 4

A field effect transistor as claimed in claim 1, wherein each of said planar-doped layers has a thickness which is substantially equal to a size of one atom of said doped impurity.

Claim 5

A field effect transistor as claimed in claim 2, wherein each of said planar-doped layers has a thickness which is substantially equal to a size of one atom of said doped impurity.

Claim 6

A field effect transistor as claimed in claim 2, wherein said internal is about 68-70 Å.

Claim 7

A field effect transistor as claimed in claim 1, wherein a large majority of carriers are present at a center of said internal between said two planar-doped layers.

Claim 8

A field effect transistor as claimed in claim 2, wherein an upper one of said two planar-doped layers is located 100 to 500 Åbelow the surface of said channel region.

Claim 9

A field effect transistor as claimed in claim 2, wherein said compound semiconductor layer is a GaAs layer.

Claim 10

A field effect transistor as claimed in claim 8, wherein said GaAs layer is an GaAs epitaxial layer formed on a semi-insulating GaAs substrate.

Claim 11

A field effect transistor as claimed in claim 8, wherein said doped impurity is selected from a group consisting of Si, Se, and S.

Claim 12

A field effect transistor as claimed in claim 8, wherein a material of said gate is selected from a group consisting of Al, Ti-Al, and W-Si.

Claim 13

A field effect transistor as claimed in claim 2, wherein said compound semiconductor layer is selected from a group consisting of an InP layer formed on an InP semi-insulating substrate and an InGaAs layer formed on an InP semi-insulating substrate.

Claim 14

A field effect transistor as claimed in claim 12, wherein said doped impurity is Si.

Claim 15

A field effect transistor comprising: a semiconductor substrate; a semiconductor channel region formed on said semiconductor substrate; a source and a drain located on opposite sides of said channel region; a gate electrode formed on the surface of said channel region; a first atomic planar-doped layer formed within said channel region at a first depth from said surface of said channel region and extending between said source and said drain; and a second atomic planar-doped layer formed within said channel region at a second depth from said surface of said channel region and extending between said source and said drain in parallel with said first atomic planar-doped layer, said second depth being deeper than said first depth and the distance between said first and second atomic planar-doped layers being equal to or smaller than substantially 70 Å.

Claim 16

A field effect transistor comprising: a semiconductor substrate; a semiconductor channel region formed on said semiconductor substrate; a source and a drain located on opposite sides of said channel region; a gate electrode formed on the surface of said channel region; a first atomic planar-doped layer formed within said channel region at a first depth from said surface of said channel region and extending between said source and said drain; and a second atomic planar-doped layer formed within said channel region at a second depth from said surface of said channel region and extending between said source and said drain in parallel with said first atomic planar-doped layer, said second depth being deeper than said first depth and the distance between said first and second atomic planar-doped layers being equal to or smaller than substantially 70 Å.

Claim 17

A field effect transistor as claimed in claim 14, wherein said semiconductor substrate is a compound semiconductor substrate, said semiconductor channel region being a compound channel region.

Claim 18

A field effect transistor as claimed in claim 14, wherein each of said atomic planar-doped layers has a thickness which is substantially equal to a size of one atom.

Claim 19

A field effect transistor as claimed in claim 15, wherein each of said atomic planar-doped layers has a thickness which is substantially equal to a size of one atom.

Claim 20

A field effect transistor as claimed in claim 15, wherein said distance between said first and second atomic planar-doped layers is about 68-70 Å.

Claim 21

A field effect transistor as claimed in claim 14, wherein a large majority of carriers are present at a center portion between said first and second atomic planar-doped layers.

Claim 22

A field effect transistor as claimed in claim 15, wherein said first depth is in the range of approximately 100 to 500 Å.

Claim 23

A field effect transistor as claimed in claim 15, wherein said compound semiconductor channel region is a GaAs channel region.

Claim 24

A field effect transistor as claimed in claim 21, wherein said compound semiconductor substrate is a semi-insulating GaAs substrate.

Claim 25

A field effect transistor as claimed in claim 21, wherein an impurity doped into said first and second atomic planar-doped layers is selected from a group consisting of Si, Se, and S.

Claim 26

A field effect transistor as claimed in claim 21, wherein a material of said gate is selected from a group consisting of Al, Ti-Al, and W-Si.

Claim 27

A field effect transistor as claimed in claim 15, wherein said compound semiconductor substrate is an InP semi-insulating substrate, said compound semiconductor channel region being selected from a group consisting of an InP channel region and an InGaAs channel region.

Claim 28

A field effect transistor as claimed in claim 25, wherein an impurity doped in said first and second planar-doped layers is Si.