Static random access memory

Claim 2

A static random access memory comprising: paired bit lines; a plurality of static memory cells connected in parallel between said paired bit lines; a write means coupled with said bit lines and for supplying write data to said bit lines; a read means coupled with said bit lines and for sensing data on the basis of the potentials on said bit lines; a data output means coupled with said read means and for outputting the data sensed by said read means; a control signal terminal supplied with a write control signal, when data is written into said plurality of memory cells, said write control signal being set at a first level, and after the data write is completed, said write control signal being set at a second level; a pulse generating means for generating a pulse signal with a given pulse width in response to a level change in said write control signal from the first level to the second level; a pulse extension means for extending the pulse width of the pulse signal generated by said pulse generating means; a first switching element connected between said bit lines, said first switching element being turned on and off by said pulse signal; second and third switching elements respectively connected between said bit lines and applied points of power source potentials, said second and third switching elements being turned on and off by said pulse signal; and a gate circuit connected between said read means and said data output means and for controlling the supply of sensed data from said read means to said data output means according to the pulse signal extended by said pulse extension means.

Claim 3

A static random access memory according to claim 1, in which said first switching element is connected between paired data lines through said paired bit lines and a switching element, and said second and third switching elements are respectively connected between said paired data lines and the applied points of power source potential.

Claim 4

A static random access memory according to claim 1, in which said first to third switching elements are MOS transistors.

Claim 5

A static random access memory according to claim 1, in which said control signal terminal is supplied with a write enable signal, when data is written into said plurality of memory cells, said write enable signal being set at a low level, and after the data write is completed, said write enable signal being set at a high level.

Claim 6

A static random access memory according to claim 1, in which said pulse generating means includes an odd number of inverting circuits connected in tandem, the first stage of said inverting circuits receiving the write control signal supplied to said control signal terminal and an AND gate supplied with the output signal from the final stage of said inverting circuits and the write control signal supplied to said control signal terminal.

Claim 7

A static random access memory according to claim 1, in which said pulse extension means includes an even number of inverting circuits connected in tandem, the first stage of said inverting circuits receiving the pulse signal from said pulse generating means, and a NOR gate supplied with the pulse signal from the final stage of said inverting circuits and said pulse generating means.

Claim 8

A static random access memory according to claim 1, in which said gate circuit includes two AND gates coupled for reception with the complementary data output from said read means and the pulse signal extended by said pulse extension means.

Claim 9

A static random access memory according to claim 1, in which said pulse extension means extends the pulse width of the pulse signal generated by said pulse generating means by a time period from an instant that data is read out from one of said plurality of memory cells till said read means operates to complementary data.

Claim 10

A static random access memory according to claim 1, in which said pulse extension means extends the pulse width of the pulse signal generated by said pulse generating means, and inverts a logical state of the extended pulse signal with respect to the pulse signal generated by said pulse generating means.

Claim 11

A static random access memory comprising: paired bit lines; a plurality of static memory cells connected in parallel between said paired bit lines; paired data lines; first and second switching elements respectively connected between said paired bit lines and said data lines, said first and second switching elements being turned on and off by a column decode signal; a write means coupled with said data lines and for supplying write data to said data lines; a read means coupled with said data lines and for sensing data on the basis of the potentials on said data lines; a data output means coupled with said read means and for outputting the data sensed by said read means; a control signal terminal supplied with a write control signal, when data is written into said plurality of memory cells, said write control signal being set at a first level, and after the data write is completed, said write control signal being set at a second level; a pulse generating means for generating a pulse signal with a given pulse width in response to a level change in said write control signal from the first level to the second level; a pulse extension means for extending the pulse width of the pulse signal generated by said pulse generating means; a third switching element connected between said bit lines, said third switching element being turned on and off by said pulse signal generated by said pulse generating means; fourth and fifth switching elements respectively connected between said bit lines and applied points of power source potentials, said fourth and fifth switching elements being turned on and off by said pulse signal generated by said pulse generating means; and a sixth switching element connected between said paired data lines, said sixth switching element being turned on and off by said pulse signal generated by said pulse generating means; seventh and eighth switching elements respectively connected between said data lines and applied points of power source potentials, said seventh and eighth switching elements being turned on and off by said pulse signal generated by said pulse generating means; and a gate circuit connected between said read means and said data output means and for controlling the supply of sensed data from said read means to said data output means according to the pulse signal extended by said pulse extension means.

Claim 12

A static random access memory comprising: paired bit lines; a plurality of static memory cells connected in parallel between said paired bit lines; paired data lines; first and second switching elements respectively connected between said paired bit lines and said data lines, said first and second switching elements being turned on and off by a column decode signal; a write means coupled with said data lines and for supplying write data to said data lines; a read means coupled with said data lines and for sensing data on the basis of the potentials on said data lines; a data output means coupled with said read means and for outputting the data sensed by said read means; a control signal terminal supplied with a write control signal, when data is written into said plurality of memory cells, said write control signal being set at a first level, and after the data write is completed, said write control signal being set at a second level; a pulse generating means for generating a pulse signal with a given pulse width in response to a level change in said write control signal from the first level to the second level; a pulse extension means for extending the pulse width of the pulse signal generated by said pulse generating means; a third switching element connected between said bit lines, said third switching element being turned on and off by said pulse signal generated by said pulse generating means; fourth and fifth switching elements respectively connected between said bit lines and applied points of power source potentials, said fourth and fifth switching elements being turned on and off by said pulse signal generated by said pulse generating means; and a sixth switching element connected between said paired data lines, said sixth switching element being turned on and off by said pulse signal generated by said pulse generating means; seventh and eighth switching elements respectively connected between said data lines and applied points of power source potentials, said seventh and eighth switching elements being turned on and off by said pulse signal generated by said pulse generating means; and a gate circuit connected between said read means and said data output means and for controlling the supply of sensed data from said read means to said data output means according to the pulse signal extended by said pulse extension means.

Claim 13

A static random access memory according to claim 10, in which said first to eighth switching elements are MOS transistors.

Claim 14

A static random access memory according to claim 10, in which said control signal terminal is supplied with a write enable signal, when data is written into said plurality of memory cells, said write enable signal being set at a low level, and after the data write is completed, said write enable signal being set at a high level.

Claim 15

A static random access memory according to claim 10, in which said pulse generating means includes an odd number of inverting circuits connected in tandem, the first stage of said inverting circuits receiving the write control signal supplied to said control signal terminal, and an AND gate supplied with the output signal from the final stage of said inverting circuits and the write control signal supplied to said control signal terminal.

Claim 16

A static random access memory according to claim 10, in which said pulse extension means includes an even number of inverting circuits connected in tandem, the first stage of said inverting circuits receiving the pulse signal from said pulse generating means, and a NOR gate supplied with the pulse signal from the final stage of said inverting circuits and said pulse generating means.

Claim 17

A static random access memory according to claim 10, in which said gate circuit includes two AND gates coupled for reception with the complementary data output from said read means and the pulse signal extended by said pulse extension means.

Claim 18

A static random access memory according to claim 10, in which said pulse extension means extends the pulse width of the pulse signal generated by said pulse generating means by a time period from an instant that data is read out from one of said plurality of memory cells till said read means operates to complementary data.

Claim 19

A static random access memory according to claim 10, in which said pulse extension means extends the pulse width of the pulse signal generated by said pulse generating means, and inverts a logical state of the extended pulse signal with respect to the pulse signal generated by said pulse generating means.