US4939478A
Expired / Lapsed
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Asymmetrical differential amplifier as level converter
Assignee: Siemens AG
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Filing: 1988-12-12
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Granted: 1990-07-03
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Expires: 2008-12-12
Abstract
Abstract An asymmetrical differential amplifier as a level converter has two transistors, a constant current source and two resistors, whereby the first transistor is a MOS transistor and the second transistor is a bipolar npn transistor. Input signals having CMOS level can be applied to an input on the input side of the differential amplifier, whereas output signals having ECL level can be taken at an output. In addition to being a differential amplifier, the circuit also produces a level conversion between CMOS level at the input side and ECL level at the output side.
Inventors
- 👤 Wolfgang Heimsch
- 👤 Ernst Muellner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:52
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/0175; H03K19/017509; H03K19/017518; H03K19/017527
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
200 words
An asymmetrical differential amplifier having a first and a second transistor, a constant current source and first and second resistors, whereby a first terminal of the first transistor and a first terminal of the second transistor are connected in common to a first circuit terminal via the constant current source and a second terminal of the first transistor is connected to a second circuit terminal via the first resistor and a second terminal of the second transistor is connected to the second circuit terminal via the second resistor, a first input is connected to a control terminal of the first transistor, a second input (V ref ) is connected to a control terminal of the second transistor and a first output (A) is connected to the second terminal of the first transistor and a second output (A) is connected to the second terminal of the second transistor, comprising the first transistor being a MOS transistor and the second transistor being a bipolar transistor; input signals for the MOS transistor being received on the first input and a reference signal that lies between a maximum and minimum of the input signals for the MOS transistor being received on the second input.
Claim 2
Dependent Claim
200 words
An asymmetrical differential amplifier having a first and a second transistor, a constant current source and first and second resistors, whereby a first terminal of the first transistor and a first terminal of the second transistor are connected in common to a first circuit terminal via the constant current source and a second terminal of the first transistor is connected to a second circuit terminal via the first resistor and a second terminal of the second transistor is connected to the second circuit terminal via the second resistor, a first input is connected to a control terminal of the first transistor, a second input (V ref ) is connected to a control terminal of the second transistor and a first output (A) is connected to the second terminal of the first transistor and a second output (A) is connected to the second terminal of the second transistor, comprising the first transistor being a MOS transistor and the second transistor being a bipolar transistor; input signals for the MOS transistor being received on the first input and a reference signal that lies between a maximum and minimum of the input signals for the MOS transistor being received on the second input.
Claim 3
Dependent Claim
26 words
The asymmetrical differential amplifier according to claim 1, wherein the first transistor is an n-channel MOS transistor and the second transistor is an npn bipolar transistor.
Claim 4
Dependent Claim
60 words
The asymmetrical differential amplifier according to claim 1, wherein the first transistor is a p-channel MOS transistor and the second transistor is an npn bipolar transistor and the first output (A) supplies a non-inverted output signal with respect to the input signal and the second output (A) supplies a further output signal inverted with respect to the non-inverted output signal.
Claim 5
Dependent Claim
86 words
The asymmetrical differential amplifier according to claim 1, wherein the constant current source has a further bipolar npn transistor; wherein a base terminal of the further npn transistor is connected to a fixed voltage (V ex ), an emitter terminal of the further bipolar npn transistor is connected to the first circuit terminal via a third resistor and a collector terminal of the further bipolar npn transistor is connected to the first terminal of the first transistor and to the first terminal of the second transistor.
Claim 6
Dependent Claim
77 words
The asymmetrical differential amplifier according to claim 1, wherein the constant current source is an n-channel MOS transistor; wherein a first terminal of the n-channel MOS transistor is connected to the first circuit terminal, a second terminal of the n-channel MOS transistor is connected to the first terminal of the first transistor and to the first terminal of the second transistor; and wherein a gate terminal of the n-channel MOS transistor is connected to a fixed voltage.
Claim 7
Dependent Claim
28 words
The asymmetrical differential amplifier according to claim 1, wherein the first circuit terminal is connected to ground and the second circuit terminal is connected to a supply voltage.
Claim 8
Dependent Claim
274 words
An asymmetrical differential amplifier having a first and a second transistor, a constant current source and first and second resistors, whereby a first terminal of the first transistor and a first terminal of the second transistor are connected in common to a first circuit terminal via the constant current source and a second terminal of the first transistor is connected to a second circuit terminal via the first resistor and a second terminal of the second transistor is connected to the second circuit terminal via the second resistor, a first input is connected to a control terminal of the first transistor, a second input (V ref ) is connected to a control terminal of the second transistor and a first output (A) is connected to the second terminal of the first transistor and a second output (A) is connected to the second terminal of the second transistor, comprising the first transistor being a MOS transistor and the second transistor being a bipolar transistor; input signals for the MOS transistor being received on the first input and a reference signal that lies between a maximum and minimum of the input signals for the MOS transistor being received on the second input; and the constant current source having a further bipolar npn transistor, a base terminal of the further npn transistor connected to a fixed voltage (V ex ), an emitter terminal of the further bipolar npn transistor connected to the first circuit terminal via a third resistor and a collector terminal of the further bipolar npn transistor connected to the first terminal of the first transistor and to the first terminal of the second transistor.
Claim 9
Dependent Claim
274 words
An asymmetrical differential amplifier having a first and a second transistor, a constant current source and first and second resistors, whereby a first terminal of the first transistor and a first terminal of the second transistor are connected in common to a first circuit terminal via the constant current source and a second terminal of the first transistor is connected to a second circuit terminal via the first resistor and a second terminal of the second transistor is connected to the second circuit terminal via the second resistor, a first input is connected to a control terminal of the first transistor, a second input (V ref ) is connected to a control terminal of the second transistor and a first output (A) is connected to the second terminal of the first transistor and a second output (A) is connected to the second terminal of the second transistor, comprising the first transistor being a MOS transistor and the second transistor being a bipolar transistor; input signals for the MOS transistor being received on the first input and a reference signal that lies between a maximum and minimum of the input signals for the MOS transistor being received on the second input; and the constant current source having a further bipolar npn transistor, a base terminal of the further npn transistor connected to a fixed voltage (V ex ), an emitter terminal of the further bipolar npn transistor connected to the first circuit terminal via a third resistor and a collector terminal of the further bipolar npn transistor connected to the first terminal of the first transistor and to the first terminal of the second transistor.
Claim 10
Dependent Claim
28 words
The asymmetrical differential amplifier according to claim 7, wherein the first circuit terminal is connected to ground and the second circuit terminal is connected to a supply voltage.
Claim 11
Dependent Claim
26 words
The asymmetrical differential amplifier according to claim 7, wherein the first transistor is an n-channel MOS transistor and the second transistor is an npn bipolar transistor.
Claim 12
Dependent Claim
60 words
The asymmetrical differential amplifier according to claim 7, wherein the first transistor is a p-channel MOS transistor and the second transistor is an npn bipolar transistor and the first output (A) supplies a non-inverted output signal with respect to the input signal and the first output (A) supplies a further output signal inverted with respect to the non-inverted output signal.
Claim 13
Dependent Claim
267 words
An asymmetrical differential amplifier having a first and a second transistor, a constant current source and first and second resistors, whereby a first terminal of the first transistor and a first terminal of the second transistor are connected in common to a first circuit terminal via the constant current source and a second terminal of the first transistor is connected to a second circuit terminal via the first resistor and a second terminal of the second transistor is connected to the second terminal via the second resistor, a first input is connected to a control terminal of the first transistor, a second input (V ref ) is connected to a control terminal of the second transistor and a first output (A) is connected to the second terminal of the first transistor and a second output (A) is connected to the second terminal of the second transistor, comprising the first transistor being a MOS transistor and the second transistor being a bipolar transistor; input signals for the MOS transistor being received on the first input and a reference signal that lies between a maximum and minimum of the input signals for the MOS transistor being received on the second input; the constant current source is a n-channel MOS transistor; where in a first terminal of the n-channel transistor is connected to the first circuit terminal, a second terminal of the n-channel MOS transistor is connected to the first terminal of the first transistor and to the first terminal of the second transistor; and wherein a gate terminal of the n-channel MOS transistor is connected to the fixed voltage.
Claim 14
Dependent Claim
267 words
An asymmetrical differential amplifier having a first and a second transistor, a constant current source and first and second resistors, whereby a first terminal of the first transistor and a first terminal of the second transistor are connected in common to a first circuit terminal via the constant current source and a second terminal of the first transistor is connected to a second circuit terminal via the first resistor and a second terminal of the second transistor is connected to the second terminal via the second resistor, a first input is connected to a control terminal of the first transistor, a second input (V ref ) is connected to a control terminal of the second transistor and a first output (A) is connected to the second terminal of the first transistor and a second output (A) is connected to the second terminal of the second transistor, comprising the first transistor being a MOS transistor and the second transistor being a bipolar transistor; input signals for the MOS transistor being received on the first input and a reference signal that lies between a maximum and minimum of the input signals for the MOS transistor being received on the second input; the constant current source is a n-channel MOS transistor; where in a first terminal of the n-channel transistor is connected to the first circuit terminal, a second terminal of the n-channel MOS transistor is connected to the first terminal of the first transistor and to the first terminal of the second transistor; and wherein a gate terminal of the n-channel MOS transistor is connected to the fixed voltage.
Claim 15
Dependent Claim
28 words
The asymmetrical differential amplifier according to claim 11, wherein the first circuit terminal is connected to ground and the second circuit terminal is connected to a supply voltage.
Claim 16
Dependent Claim
55 words
The asymmetrical differential amplifier according to claim 12, wherein the first transistor is an n-channel MOS transistor and the second transistor is an npn bipolar transistor and wherein the second output (A) supplies a non-inverted output signal and the first output (A) supplies a further output signal inverted with respect to the non-inverted output signal.
Claim 17
Dependent Claim
60 words
The asymmetrical differential amplifier according to claim 12, wherein the first transistor is a p-channel MOS transistor and the second transistor is an npn bipolar transistor and the first output (A) supplies a non-inverted output signal with respect to the input signal and the first output (A) supplies a further output signal inverted with respect to the non-inverted output signal.
References Cited (Backward Citations)
US4782251A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-02 | 1994-01-01 | 1994-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-02 | 1998-01-01 | 1998-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-02 | 2002-01-01 | 2002-07-03 | $7700.00 | Window Closed / Lapsed |