Synchronous circuit system having asynchronous signal input

Claim 2

A synchronous circuit system comprising: switch circuit means having an input for receiving an asynchronous input signal and being responsive to a synchronizing signal for transmitting said asynchronous input signal only within a specified time period as determined by the logic state of the synchronizing signal; latch circuit means connected to said switch circuit means for receiving said asynchronous input signal when transmitted by said switch circuit means and latching the data imparted by said asynchronous input signal in a logic state of one of a high logic state and a low logic state; signal transmission circuit means connected to the output of said latch circuit means and holding the logic state of the latched data until a predetermined input level of said asynchronous input signal is attained for reception by said latch circuit means, said signal transmission means providing an output; and feedback circuit means connected between the output of said signal transmission circuit means and the output of said switch circuit means to enable stable operation to be accomplished even though an asynchronous input signal may appear at the only unstable point in said latch circuit means.

Claim 3

A synchronous circuit system as set forth in claim 1, wherein said signal transmission circuit means comprises a Schmitt-trigger circuit means.

Claim 4

A synchronous circuit system as set forth in claim 2, wherein said switch circuit means includes an MOS transistor having a gate and being rendered conductive in response to a predetermined logic state of a synchronizing signal applied to said gate for transmitting said asynchronous input signal only during the time said MOS transistor is conductive.

Claim 5

A synchronous circuit system as set forth in claim 2, wherein said latch circuit means comprises a pair of inverters connected together in a positive feedback connection to the output of said switch circuit means; and said feedback circuit means including a second MOS transistor having a gate, said second MOS transistor being connected to the positive feedback connection of said latch circuit means at the output of said switch circuit means.

Claim 6

A synchronous circuit system as set forth in claim 4, wherein one of said inverter pair of said latch circuit means receiving the output of said switch circuit means has a threshold voltage (V th1 ) higher than 1/2 of the voltage (V DD ) applied to said synchronous circuit system, and the other inverter of said latch circuit means has a threshold voltage (V th2 ) lower than 1/2 of the voltage (V DD ); and the threshold voltage (V th3 ) of said Schmitt-trigger circuit means is set to be higher than the threshold voltage of said other inverter (V th2 ) of said latch circuit means and to be >1/2 of the voltage (V DD ).

Claim 7

A synchronous circuit system as set forth in claim 5, further including a third inverter connected to the output of said Schmitt-trigger circuit means; an MOS output transistor connected to said third inverter at the output of said Schmitt-trigger circuit means; and said feedback circuit means further including a fourth inverter and a feedback conductor line, said feedback conductor line being connected at one end thereof between the third inverter at the output of said Schmitt-trigger circuit means and said MOS output transistor and at the other end thereof to said output of said switch circuit means and having said fourth inverter and said second MOS transistor serially disposed therein.

Claim 8

A synchronous circuit system as set forth in claim 4, wherein one of said inverter pair of said latch circuit means receiving the output of said switch circuit means has a threshold voltage (V th1 ) lower than 1/2 of the voltage (V DD ) applied to said synchronous circuit system, and the other inverter of said latch circuit means has a threshold voltage (V th2 ) higher than 1/2 of the voltage (V DD ); and the threshold voltage (V th3 ) of said Schmitt-trigger circuit means is set to be lower than the threshold voltage of said other inverter (V th2 ) of said latch circuit means and to be <1/2 of the voltage (V DD ).

Claim 9

A synchronous circuit system as set forth in claim 7, further including a third inverter connected to the output of said Schmitt-trigger circuit means; an MOS output transistor connected to said third inverter at the output of said Schmitt-trigger circuit means; and said feedback circuit means further including a fourth inverter and a feedback conductor line, said feedback conductor line being connected at one end thereof between the third inverter at the output of said Schmitt-trigger circuit means and said MOS output transistor and at the other end thereof to said output of said switch circuit means and having said fourth inverter and said second MOS transistor serially disposed therein.

Claim 10

A synchronous circuit system comprising: switch circuit means having an input for receiving an asynchronous input signal and including a CMOS transistor responsive to a synchronizing signal for being rendered conductive to transmit said asynchronous input signal only within the time period that said CMOS transistor is conductive; latch circuit means connected to said switch circuit means for receiving said asynchronous input signal when transmitted by said switch circuit means and comprising a pair of inverters connected together in a positive feedback connection to the output of said switch circuit means for latching the data imparted by said asynchronous input signal in a logic state of one of a high logic state and a low logic state; and feedback circuit means connected between the output of said latch circuit means and the output of said switch circuit means to enable stable operation to be accomplished even though an asynchronous input signal may appear at the only unstable point in said latch circuit means, said feedback circuit means including an inverter having a high threshold voltage, a CMOS transistor, and a feedback conductor line, said feedback conductor line being connected between the output of said latch circuit means and the output of said switch circuit means and having said inverter and said CMOS transistor of said feedback circuit means serially disposed therein.

Claim 11

A synchronous circuit system comprising: switch circuit means having an input for receiving an asynchronous input signal and including a CMOS transistor responsive to a synchronizing signal for being rendered conductive to transmit said asynchronous input signal only within the time period that said CMOS transistor is conductive; latch circuit means connected to said switch circuit means for receiving said asynchronous input signal when transmitted by said switch circuit means and comprising a pair of inverters connected together in a positive feedback connection to the output of said switch circuit means for latching the data imparted by said asynchronous input signal in a logic state of one of a high logic state and a low logic state; and feedback circuit means connected between the output of said latch circuit means and the output of said switch circuit means to enable stable operation to be accomplished even though an asynchronous input signal may appear at the only unstable point in said latch circuit means, said feedback circuit means including an inverter having a high threshold voltage, a CMOS transistor, and a feedback conductor line, said feedback conductor line being connected between the output of said latch circuit means and the output of said switch circuit means and having said inverter and said CMOS transistor of said feedback circuit means serially disposed therein.

Claim 12

A synchronous circuit system as set forth in claim 9, further including an MOS output transistor connected to the output of said latch circuit means and having a gate responsive to a signal applied thereto for being rendered conductive to transmit the output from said latch circuit means as an output signal.

Claim 13

A snychronous circuit system as set forth in claim 10, wherein the signal applied to the gate of said MOS output transistor is a control signal different from the synchronizing signal.