Method and circuitry for carrier recovery for time division multiple access radio systems

Claim 3

The method of claim 1, wherein said first and second phase-lock loops are each first-order loops.

Claim 4

The method of claim 2, wherein said first and second phase-lock loops each have a gain of 2 -n , where n is a positive integer.

Claim 5

The method of claim 3, wherein n=2.

Claim 6

The method of claim 1, wherein said first and second portions are each approximately one-half of said signal burst.

Claim 7

The method of claim 1, wherein said first portion of said signal burst is stored in step (b) at least at symbol rate.

Claim 8

The method of claim 6, wherein said symbol rate is approximately in a range between 100 K and 1 Mega baud.

Claim 9

The method of claim 1, wherein demodulated portions of said signal burst in step (d) are fed into a reordering random access memory for reordering in accordance with step (e).

Claim 10

The method of claim 8, wherein the demodulated first portion of said signal burst which is stored in said reordering random access memory is reordered in accordance with step (e) by reading said reordering random access memory backwards for said first portion.

Claim 11

The method of claim 9, wherein the demodulated second portion of said signal burst which is stored in said reordering random access memory is forwardly read from said reordering random access memory after reading said first portion.

Claim 12

The method of claim 2, wherein said first-order, phase-lock loops are each modified by a previous estimate of frequency offset of said carrier, and wherein said method further comprises the steps of: (f) obtaining a phase increment at a sample rate; and (g) adding said phase increment to a feed-back signal of said first-lock loop, and subtracting said phase increment from a feed-back signal of said second phase-lock.

Claim 13

A circuit for processing a burst of symbols for obtaining carrier recovery in a time division multiple access radio system comprising: a first storage means for receiving and storing a first portion of a signal burst; a first phase-lock loop for tracking and acquiring carrier phase; a second phase-lock loop operatively connected to said first phase-lock loop and said first storage means for tracking and acquiring carrier phase with said first phase-lock loop during said first portion of said signal burst; means for feeding at the end of said first portion of said signal burst said stored first portion from said first storage means into said second phase-lock loop in reverse order of reception during a demodulation phase, said second phase-lock loop initially having at the end of said first portion the same phase state as the then phase state of the first phase-lock loop; means for initiating demodulation of said signal burst at the end of said first portion, wherein said second phase-lock loop backwardly demodulates said stored first portion of said signal burst while said first phase-lock loop demodulates a remaining second portion of said signal burst; and a reordering storage means operatively connected to said first and second phase-lock loops for receiving and storing said first and second demodulated portions of said signal burst.

Claim 14

A circuit for processing a burst of symbols for obtaining carrier recovery in a time division multiple access radio system comprising: a first storage means for receiving and storing a first portion of a signal burst; a first phase-lock loop for tracking and acquiring carrier phase; a second phase-lock loop operatively connected to said first phase-lock loop and said first storage means for tracking and acquiring carrier phase with said first phase-lock loop during said first portion of said signal burst; means for feeding at the end of said first portion of said signal burst said stored first portion from said first storage means into said second phase-lock loop in reverse order of reception during a demodulation phase, said second phase-lock loop initially having at the end of said first portion the same phase state as the then phase state of the first phase-lock loop; means for initiating demodulation of said signal burst at the end of said first portion, wherein said second phase-lock loop backwardly demodulates said stored first portion of said signal burst while said first phase-lock loop demodulates a remaining second portion of said signal burst; and a reordering storage means operatively connected to said first and second phase-lock loops for receiving and storing said first and second demodulated portions of said signal burst.

Claim 15

The circuit of claim 12, wherein said circuit is an integrated circuit.

Claim 16

The circuit of claim 12, wherein said first and second phase-lock loops are each first-order loops.

Claim 17

The circuit of claim 14, wherein said first and second phase-lock loops each have a gain of 2 -n , where n is a positive integer.

Claim 18

The circuit of claim 15, wherein n=2.

Claim 19

The circuit of claim 12, wherein said first storage means receives and stores said symbols at a symbol rate approximately in a range of between 100 K and 1 Mega baud.

Claim 20

The circuit of claim 12, wherein said first and second portions of said signal burst are each approximately one-half of said signal burst.

Claim 21

The circuit of claim 18, wherein said means for feeding said first portion of said signal burst from said first storage means to said second phase-lock loop comprises a first up/down counter operatively connected to said first storage means for addressing said storage means in a reverse direction.

Claim 22

The circuit of claim 19, further comprising a second up/down counter operatively connected to said reordering storage means for addressing said reordering storage means to provide a reading of said first portion of said stored demodulated burst in a forward direction.

Claim 23

The circuit of claim 20, wherein said second up/down counter is operatively offset in time from said first up/down counter by an amount approximately equal to a delay in said phase-lock loops.

Claim 24

The circuit of claim 21, wherein said time offset is approximately a one symbol delay.

Claim 25

The circuit of claim 12, wherein a differential decoder is operatively connected to said reordering storage means and is driven by the demodulated signal burst.

Claim 26

The circuit of claim 12, further comprising means for adding a phase increment to a feed-back signal of said first phase-lock loop.

Claim 27

The circuit of claim 12, further comprising means for subtracting a phase increment from a feed-back signal of said second phase-lock loop.