US4937790A
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Semiconductor memory device
Assignee: Hitachi Ltd
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Filing: 1988-08-03
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Granted: 1990-06-26
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Expires: 2008-08-03
Abstract
Abstract A semiconductor memory device is disclosed, in which a word line address translation unit, a data line address translation unit, a first spare memory and a second spare memory are provided in addition to a main memory to relieve a defective memory cell in the main memory. Spare word line address signals for selecting a spare word line on the first spare memory are written in the word line address translation unit, spare data line address signals for selecting a spare data line on the second spare memory are written in the data line address translation unit, and each of the word line address translation unit and the data line address translation unit is constructed of an ordinary semiconductor memory of the multi-bit output type.
Inventors
- 👤 Toshio Sasaki
- 👤 Toshiaki Masuhara
- 👤 Osamu Minato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:56
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76; G11C29/78; G11C29/80; G11C29/808
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
618 words
A semiconductor memory device comprising: an I/O terminal; a main memory having a plurality of memory cells, one of the memory cells being selected in accordance with word line address signals and data line address signals; first and second spare memories for relieving a fault in the main memory; a word line address translation unit applied with the word line address signals for delivering spare word line address signals from a first output portion of the unit to the first spare memory, and for delivering a word line fault detection signal which indicates that a defective memory cell relating to the word line address signals is present in the main memory from a second output portion of the unit; a data line address translation unit applied with the data line address signals for delivering spare data line address signals from a first output portion of the unit to the second spare memory, and for delivering a data line fault detection signal which indicates that a defective memory cell relating to the data line address signals is present in the main memory from a second output portion of the unit; an input/output changeover circuit having a first terminal coupled with an input/output terminal of the main memory and a second terminal coupled to input/output terminals of the first and second spare memories and a third terminal coupled to the I/O terminal; and a control circuit having inputs which respond to the word line fault detection signal and the data line fault detection signal, and having an output which controls the input/output changeover circuit, wherein the data line address signals are applied to the first spare memory, together with the spare word line address signals, wherein the word line address signals are applied to the second spare memory, together with the spare data line address signals, wherein in a case where neither the word line fault detection signal and the data line fault detection signal is delivered from either of the second output portions of the word line address translation unit and of the data line address translation unit, the output of the control circuit controls the input/output changeover circuit so as to form a signal transmission path between the I/O terminal and the input/output terminal of the main memory, and wherein at least one of the plurality of memory cells of the main memory is selected in accordance with the word line address signals and the data line address signals, wherein in a case where the word line fault detection signal is delivered from the second output portion of the word line address translation unit, the output of the control circuit controls the input/output changeover circuit so as to form a signal transmission path between the I/O terminal and the input/output terminal of the first spare memory, and wherein at least one of a plurality of spare memory cells of the first spare memory is selected in accordance with the spare word line address signals and the data line address signals, to relieve a fault relating to a word line in the main memory, and wherein in a case where the data line fault detection signal is delivered from the second output portion of the data line address translation unit, the output of the control circuit controls the input/output changeover circuit so as to form a signal transmission path between the I/O terminal and the input/output terminal of the second spare memory, and wherein at least one of a plurality of spare memory cells of the second spare memory is selected in accordance with the spare data line address signals and the word line address signals, to relieve a fault relating to a data line in the main memory.
Claim 2
Dependent Claim
618 words
A semiconductor memory device comprising: an I/O terminal; a main memory having a plurality of memory cells, one of the memory cells being selected in accordance with word line address signals and data line address signals; first and second spare memories for relieving a fault in the main memory; a word line address translation unit applied with the word line address signals for delivering spare word line address signals from a first output portion of the unit to the first spare memory, and for delivering a word line fault detection signal which indicates that a defective memory cell relating to the word line address signals is present in the main memory from a second output portion of the unit; a data line address translation unit applied with the data line address signals for delivering spare data line address signals from a first output portion of the unit to the second spare memory, and for delivering a data line fault detection signal which indicates that a defective memory cell relating to the data line address signals is present in the main memory from a second output portion of the unit; an input/output changeover circuit having a first terminal coupled with an input/output terminal of the main memory and a second terminal coupled to input/output terminals of the first and second spare memories and a third terminal coupled to the I/O terminal; and a control circuit having inputs which respond to the word line fault detection signal and the data line fault detection signal, and having an output which controls the input/output changeover circuit, wherein the data line address signals are applied to the first spare memory, together with the spare word line address signals, wherein the word line address signals are applied to the second spare memory, together with the spare data line address signals, wherein in a case where neither the word line fault detection signal and the data line fault detection signal is delivered from either of the second output portions of the word line address translation unit and of the data line address translation unit, the output of the control circuit controls the input/output changeover circuit so as to form a signal transmission path between the I/O terminal and the input/output terminal of the main memory, and wherein at least one of the plurality of memory cells of the main memory is selected in accordance with the word line address signals and the data line address signals, wherein in a case where the word line fault detection signal is delivered from the second output portion of the word line address translation unit, the output of the control circuit controls the input/output changeover circuit so as to form a signal transmission path between the I/O terminal and the input/output terminal of the first spare memory, and wherein at least one of a plurality of spare memory cells of the first spare memory is selected in accordance with the spare word line address signals and the data line address signals, to relieve a fault relating to a word line in the main memory, and wherein in a case where the data line fault detection signal is delivered from the second output portion of the data line address translation unit, the output of the control circuit controls the input/output changeover circuit so as to form a signal transmission path between the I/O terminal and the input/output terminal of the second spare memory, and wherein at least one of a plurality of spare memory cells of the second spare memory is selected in accordance with the spare data line address signals and the word line address signals, to relieve a fault relating to a data line in the main memory.
Claim 3
Dependent Claim
99 words
A semiconductor memory device according to claim 1, wherein the spare word line address signals for selecting a spare word line on the first spare memory and the word line fault detection signal are written in the word line address translation unit at addresses which are determined by the word line address signals, and wherein the spare data line address signals for selecting a spare data line on the second spare memory and the data line fault detection signal are written in the data line address translation unit at addresses which are determined by the data line address signals.
Claim 4
Dependent Claim
35 words
A semiconductor memory device according to claim 1, wherein each of the word line address translation unit and the data line address translation unit is constructed of a semiconductor memory of the multi-bit output type.
Claim 5
Dependent Claim
35 words
A semiconductor memory device according to claim 2, wherein each of the word line address translation unit and the data line address translation unit is constructed of a semiconductor memory of the multi-bit output type.
Claim 6
Dependent Claim
244 words
A fault relief method using the semiconductor memory device claimed in claim 1, comprising the steps of: writing the spare word line address signals for selecting a spare word line on the first spare memory and the word line fault detection signal in the word line address translation unit at a plurality of address determined by the word line address signals, and writing the spare data line address signals for selecting a spare data line on the second spare memory and the data line fault detection signal in the data line address translation unit at a plurality of addresses determined by the data line address signals; and selecting at least one of a plurality of spare memory cells of the first spare memory in accordance with the spare word line address signals and the data line address signals for a case where the word line fault detection signal is delivered from the second output portion of the word line address translation unit, to relieve a fault relating to a word line on the main memory, and selecting at least one of a plurality of spare memory cells of the second spare memory in accordance with the spare data line address signals and the word line address signals for a case where the data line fault detection signal is delivered from the second output portion of the data line address translation unit, to relieve a fault relating to a data line on the main memory.
Claim 7
Dependent Claim
35 words
A fault relief method according to claim 5, wherein each of the word line address translation unit and the data line address translation unit is constructed of a semiconductor memory of the multi-bit output type.
References Cited (Backward Citations)
US4745582A
Cited
US4817056A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-25 | 1993-12-25 | 1994-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-25 | 1997-12-25 | 1998-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-25 | 2001-12-25 | 2002-06-26 | $7700.00 | Window Closed / Lapsed |