Patent US4686504A successfully refreshed from Google Patents.
US4937643A
Expired / Lapsed
US
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Devices having tantalum silicide structures
Assignee: AT&T Inc
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Filing: 1987-07-27
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Granted: 1990-06-26
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Expires: 2007-07-27
Abstract
Abstract A method for fabricating a device which includes a tantalum silicide structure, and which is essentially free of conductive etch residues, is disclosed. The method includes the steps of depositing tantalum and silicon onto a substrate, patterning the tantalum and silicon, and then sintering the patterned tantalum and silicon to form a patterned layer of tantalum silicide.
Inventors
- 👤 Jean S. Deslauriers
- 👤 Hyman J. Levinstein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:44
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10P50/268; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
128 words
A device, comprising: a substrate including semiconductor material; and a field effect transistor (FET) including a source, a drain, a gate insulator and a gate formed in and on said substrate, said gate insulator comprising a layer of silicon oxide and said gate comprising a polysilicon layer on said gate insulator over a region of said substrate between said source and said drain, said gate including on said polysilicon a layer of tantalum silicide, CHARACTERIZED IN THAT said layer of tantalum silicide has at least one essentially vertical wall where the maximum lateral displacement of any portion of said wall relative to any other portion of said wall is less than about one-quarter the height of the wall, and said FET is essentially free of conductive etch residues.
Claim 2
Independent Claim
128 words
A device, comprising: a substrate including semiconductor material; and a field effect transistor (FET) including a source, a drain, a gate insulator and a gate formed in and on said substrate, said gate insulator comprising a layer of silicon oxide and said gate comprising a polysilicon layer on said gate insulator over a region of said substrate between said source and said drain, said gate including on said polysilicon a layer of tantalum silicide, CHARACTERIZED IN THAT said layer of tantalum silicide has at least one essentially vertical wall where the maximum lateral displacement of any portion of said wall relative to any other portion of said wall is less than about one-quarter the height of the wall, and said FET is essentially free of conductive etch residues.
References Cited (Backward Citations)
US4488166A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-25 | 1993-12-25 | 1994-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-25 | 1997-12-25 | 1998-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-25 | 2001-12-25 | 2002-06-26 | $7700.00 | Window Closed / Lapsed |