US4935912A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for digitally generating a tracking error signal to avoid offset monitoring
Assignee: Pioneer Corp
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Filing: 1988-05-23
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Granted: 1990-06-19
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Expires: 2008-05-23
Abstract
Abstract A circuit for computing a tracking error signal digitally. Under control of appropriate timing, input RF signals are latched in successive latches, and outputs of the latches are compared. The latch (9) whose output is D/A converted as a tracking error signal is controlled by suitable logic (25) to latch an output of a preceding latch (8), that output being used to provide input to the logic (25) through a threshold circuitry which includes adders (21,22) and comparators (14,15). The circuit takes advantage of servo patterns on surfaces of disks, particularly optical disks, to provide track count and on-track status. The digital approach removes the necessity for using capacitors or other types of sample-and-hold circuitry, and for controlling offset values.
Inventors
- 👤 Hiroyuki Hirano
- 👤 Akira Motoyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:38
CPC Classifications
G; G11; G11B; G11B7/00; G11B7/08; G11B7/09; G11B7/0901; G11B21/00; G11B21/02; G11B21/10; G11B21/106
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
247 words
A tracking error signal generating circuit comprising: conversion means (1) for converting an inputted analog radio frequency signal to a digital signal; timing signal generating means (2) for generating at least first through third predetermined timing signals; first, second and third latching means (3-5) for latching an output of said conversion means in synchronization with said first, second, and third predetermined timing signals, respectively; first comparator means (13) for comparing the outputs of said first and second latching means (3,4); fourth latching means (17) for latching an output of said first comparator means; selector means (18) for selecting one of the outputs of said first and second latching means in accordance with an output of said fourth latching means (17); subtractor means (19) for calculating a difference between respective outputs of said third latching and selector means (5,18); fifth latching means (8) for latching an output of said subtractor means (19); sixth latching means (9) for latching the output of said fifth latching means (8); adder means (21,22) for adding a predetermined value to an output of said sixth latching means (9); second comparator means (14,15) for comparing an output of said adder means (21,22) with the output of the fifth latching means (8); logic means (25) for controlling the sixth latching means (9) in accordance with an output of said second comparator means (14,15); and conversion means (24) for converting a digital output of said sixth latching means to provide an analog tracking error output signal.
Claim 2
Dependent Claim
247 words
A tracking error signal generating circuit comprising: conversion means (1) for converting an inputted analog radio frequency signal to a digital signal; timing signal generating means (2) for generating at least first through third predetermined timing signals; first, second and third latching means (3-5) for latching an output of said conversion means in synchronization with said first, second, and third predetermined timing signals, respectively; first comparator means (13) for comparing the outputs of said first and second latching means (3,4); fourth latching means (17) for latching an output of said first comparator means; selector means (18) for selecting one of the outputs of said first and second latching means in accordance with an output of said fourth latching means (17); subtractor means (19) for calculating a difference between respective outputs of said third latching and selector means (5,18); fifth latching means (8) for latching an output of said subtractor means (19); sixth latching means (9) for latching the output of said fifth latching means (8); adder means (21,22) for adding a predetermined value to an output of said sixth latching means (9); second comparator means (14,15) for comparing an output of said adder means (21,22) with the output of the fifth latching means (8); logic means (25) for controlling the sixth latching means (9) in accordance with an output of said second comparator means (14,15); and conversion means (24) for converting a digital output of said sixth latching means to provide an analog tracking error output signal.
Claim 3
Dependent Claim
127 words
A tracking error signal generating circuit as claimed in claim 1, wherein said adder means and said second comparator means comprise: a first adder (21) for adding a first predetermined standard value to said output of said sixth latching means (9); a first comparator (14) for comparing an output of said first adder (21) and said output of said fifth latching means (8); a second adder (22) for adding a second predetermined standard value to said output of said sixth latching means (9); a second comparator (15) for comparing an output of said second adder (22) and said output of said fifth latching means (8); wherein said logic means (25) controls said sixth latching means (9) in accordance with respective outputs of said first and second comparators.
Claim 4
Dependent Claim
29 words
A tracking error signal generating circuit as claimed in claim 1, wherein said logic means (25) controls said sixth latching means (9) in accordance with an asynchronous input signal.
Claim 5
Dependent Claim
61 words
A tracking error signal generating circuit as claimed in claim 1, further comprising zero crossing point detecting means (26) for detecting a zero crossing point of a polarity of said tracking error output signal and providing first and second outputs accordingly, and on-track output means (10,11,12,16,23) for outputting an on-track signal indicative of centering of a pickup on a track centerline.
Claim 6
Dependent Claim
153 words
A tracking error signal generating circuit as claimed in claim 4, wherein said on-track output means comprises: seventh latching means (6) for latching an output of said conversion means (1) in accordance with said timing signal generator means (2); eighth latching means (10) for latching an output of said seventh latching means (6) in accordance with said first output of said zero crossing point detecting means (26); ninth latching means (11) for latching said output of said seventh latching means (6) in accordance with said second output of said zero crossing point detecting means (26); second adder means (23) for adding respective outputs of said eighth and ninth latching means (10, 11) and outputting a mean value of said added respective outputs; tenth latching means (12) for latching said mean value; and third comparator means (16) for comparing respective outputs of said seventh and tenth latching means (6,12) and providing said on-track signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-18 | 1993-12-18 | 1994-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-18 | 1997-12-18 | 1998-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-18 | 2001-12-18 | 2002-06-19 | $7700.00 | Window Closed / Lapsed |