Pseudo-random phase shifted arithmetic bit clock generators for digital printers

Claim 1

In a digital printer including an arithmetic frequency synthesizer having an accumulator for recursively accumulating a R-bit long word of value, N, where -2 R-1 ≦N<2 R , to provide an accumuland with a most significant bit oscillating at a bit clock frequency proportional to the value N; means coupled to said frequency synthesizer for modulating a light beam at said bit clock frequency in accordance with data samples representing an image; and scanner means for repeatedly scanning the modulated light beam across a photosensitive recording medium to print said image on said recording medium in accordance with a raster scanning pattern; the improvement comprising means coupled to said frequency synthesizer for preloading pseudo-random offset values into said accumulator for successive scans, said offset values pseudo-randomly varying from scan-to-scan within a range 0≦accm i <N, where accm i is the offset value for any given scan, whereby said bit clock is pseudo-randomly phase shifted from scan-to-scan without significantly affecting its frequency.