US4935804A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Fujitsu Ltd
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Filing: 1988-03-03
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Granted: 1990-06-19
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Expires: 2008-03-03
Abstract
Abstract A semiconductor device with an electrode wiring layer including an upper conductive layer and, interspaced with a barrier layer used for reaction prevention, a lower conductive layer contacting an active region. The barrier layer consists of an insulating film having a thickness thin enough for flow of a tunnel current.
Inventors
- 👤 Takashi Ito
- 👤 Hiroshi Horie
- 👤 Toshihiro Sugii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:24
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312; H10D30/674; H10D30/6741; H10D30/6743; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/664
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
129 words
A semiconductor device comprising: a substrate; an active region formed on said substrate; and a multi-layer electrode wiring layer formed on said active region, said multi-layer electrode wiring layer including, a lower conductive layer contacting said active region, an upper conductive layer, said upper and lower conductive layers having same plane patterns and together form said multi-layer electrode wiring while coextending over the substrate, and a barrier layer disposed between said upper conductive layer and said lower conductive layer, said barrier layer being used for reaction prevention between said upper conductive layer and said lower conductive layer, said barrier layer being of an insulating film having a thickness thin enough for flow of a tunnel current to maintain said lower and upper conductive layers at a substantially same potential.
Claim 2
Dependent Claim
129 words
A semiconductor device comprising: a substrate; an active region formed on said substrate; and a multi-layer electrode wiring layer formed on said active region, said multi-layer electrode wiring layer including, a lower conductive layer contacting said active region, an upper conductive layer, said upper and lower conductive layers having same plane patterns and together form said multi-layer electrode wiring while coextending over the substrate, and a barrier layer disposed between said upper conductive layer and said lower conductive layer, said barrier layer being used for reaction prevention between said upper conductive layer and said lower conductive layer, said barrier layer being of an insulating film having a thickness thin enough for flow of a tunnel current to maintain said lower and upper conductive layers at a substantially same potential.
Claim 3
Dependent Claim
26 words
A semiconductor device according to claim 1, wherein said active region is a gate insulating film region in a gate portion of an MIS semiconductor device.
Claim 4
Dependent Claim
17 words
A semiconductor device according to claim 1, wherein said barrier layer consists of a silicon nitride film.
Claim 5
Dependent Claim
32 words
A semiconductor device according to claim 1, wherein said lower conductive layer consists of polycrystalline silicon and said upper conductive layer consists of a high melting point metal or a silicide thereof.
Claim 6
Dependent Claim
27 words
A semiconductor device according to claim 4, wherein said barrier layer comprises a direct nitride film of the lower conductive layer surface consisting of the polycrystalline silicon.
Claim 7
Dependent Claim
36 words
A semiconductor device according to claim 1, wherein said active region consists of a semiconductor region on which an ohmic electrode is arranged and said lower conductive layer is in ohmic contact with the active layer.
Claim 8
Dependent Claim
36 words
A semiconductor device according to claim 1, wherein said active region consists of a semiconductor region on which a rectifying electrode is arranged and said lower conductive layer is in rectifying contact with the active region.
References Cited (Backward Citations)
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US4117506A
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US4141022A
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US4460980A
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US4377857A
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JPS57149751A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-18 | 1993-12-18 | 1994-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-18 | 1997-12-18 | 1998-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-18 | 2001-12-18 | 2002-06-19 | $7700.00 | Window Closed / Lapsed |