Semiconductor memory device having arithmetic means

Claim 2

A semiconductor memory device formed on one chip comprising: a memory unit; an arithmetic circuit for generating an arithmetic signal to be fed to said memory unit, wherein said arithmetic circuit has a plurality of operation modes which are designated in accordance with a function signal; an input terminal; a first circuit for forming said function signal to designate one of said operation modes of said arithmetic circuit on the basis of a first input signal provided from said input terminal; a second circuit for forming a mask signal to inhibit a data signal of said memory unit from being changed by an external input data signal provided from said input terminal on the basis of a second input signal provided from said input terminal; a timing control signal to which is responsive to control signals applied thereto for generating control timing signals to cause said first and second circuits to receive said first and second input signals, respectively; and a data input circuit disposed between one input side of said arithmetic circuit and said input terminal for receiving said input data signal from said input terminal, and having its operations controlled by the mask signal fed from said second circuit, wherein said input terminal serves as a common input terminal for said first input signal, said second input signal and said input data signal.

Claim 3

A semiconductor memory device formed on one chip according to claim 1, wherein said control signals include a row address strobe signal, a column address strobe signal, and a write enable signal, and wherein said timing control signal circuit generates said control timing signals for said first and second circuits in response to the combination of an inactive level of said row address strobe signal and a write enable level of said write enable signal.

Claim 4

A semiconductor memory device formed on one chip according to claim 2, wherein said memory unit includes dynamic random access memories.

Claim 5

A semiconductor memory device formed on one chip according to claim 3, further comprising: a signal latch circuit disposed at one input side of said arithmetic circuit for latching a data signal fed from said memory unit; and a data input circuit disposed at another input side of said arithmetic circuit and having its operations controlled by the mask signal fed from said second circuit.

Claim 6

A semiconductor memory device formed on one chip according to claim 2, wherein said control signals further include an additional control signal, so that the control timing signal for said first circuit and the control timing signal for said second circuit have their respective outputs controlled by said additional control signal.

Claim 7

A semiconductor memory device formed on one chip according to claim 1, wherein said control signals include a row address strobe signal, a column address strobe signal, a write enable signal, and an additional control signal, and wherein said timing control signal circuit generates a control timing signal in said timing signals for said second circuit in response to a combination of conditions in which said write enable signal has a first level, said additional control signal has said first level, and a level of said row address strobe signal is changed from a second level to said first level.

Claim 8

A semiconductor memory device formed on one chip according to claim 6, wherein said timing control signal circuit generates a control timing signal in said timing signals for said first circuit in response to a combination of conditions in which said additional control signal has said second level and a level of said column address strobe signal is changed from said second level to said first level.

Claim 9

A semiconductor memory device formed on one chip according to claim 4, wherein said input terminal is coupled to an input node of said data input circuit, and said first and second circuits are coupled to said input terminal.

Claim 10

A single chip semiconductor memory device for processing high-speed image data comprising: a memory unit on one semiconductor substrate; arithmetic means on said substrate for generating arithmetic signals to be fed to said memory unit wherein said arithmetic means has a plurality of operation modes which are designated in accordance with function signals; input terminals; first circuit means on said substrate for forming said function signals to designate one of said operation modes in said arithmetic circuit means on the basis of first input signals provided from said input terminals; second circuit means on said substrate for forming mask signals to inhibit data signals of said memory unit from being changed by external input data signals provided from said input terminals on the basis of second input signals provided from said input terminals; timing control circuit means on said substrate responsive to control signals for generating control timing signals to cause said respective first and second circuit means to receive said first and second input signals; and a data input circuit disposed between one input side of said arithmetic circuit and said input terminals for receiving input data signals from said input terminals, and having its operations controlled by the mask signal fed from said second circuit, wherein each of said input terminals serves as a common input terminal for one of said first input signals, one of said second input signals and one of said input data signals.

Claim 11

A single chip semiconductor memory device for processing high-speed image data comprising: a memory unit on one semiconductor substrate; arithmetic means on said substrate for generating arithmetic signals to be fed to said memory unit wherein said arithmetic means has a plurality of operation modes which are designated in accordance with function signals; input terminals; first circuit means on said substrate for forming said function signals to designate one of said operation modes in said arithmetic circuit means on the basis of first input signals provided from said input terminals; second circuit means on said substrate for forming mask signals to inhibit data signals of said memory unit from being changed by external input data signals provided from said input terminals on the basis of second input signals provided from said input terminals; timing control circuit means on said substrate responsive to control signals for generating control timing signals to cause said respective first and second circuit means to receive said first and second input signals; and a data input circuit disposed between one input side of said arithmetic circuit and said input terminals for receiving input data signals from said input terminals, and having its operations controlled by the mask signal fed from said second circuit, wherein each of said input terminals serves as a common input terminal for one of said first input signals, one of said second input signals and one of said input data signals.

Claim 12

A single chip semiconductor memory device for processing high-speed image data according to claim 9, wherein said control signals include a row address strobe signal, a column address strobe signal, a write enable signal, and an additional control signal, and wherein said timing control circuit means generates a control timing signal in said timing signals for said second circuit means in response to a combination of conditions in which said write enable signal has a first level, said additional control signal has said first level, and a level of said row address strobe signal is changed from a second level to said first level.

Claim 13

A single chip semiconductor memory device for processing high-speed image data according to claim 10, wherein said timing control circuit means generates a control timing signal in said timing signals for said first circuit means in response to a combination of conditions in which said additional control signal has a second level and a level of said column address strobe signal is changed from said second level to said first level.

Claim 14

A single chip semiconductor memory device for processing high-speed image data according to claim 9, wherein said control signals include a row address strobe signal, a column address strobe signal, and a write enable signal, and said timing control circuit means generates said control timing signals for said first and second circuit means in response to the combination of an inactive level of said row address strobe signal and a write enable level of said write enable signal.

Claim 15

A single chip semiconductor memory device for processing high-speed image data according to claim 12, wherein said control signals further include an additional control signal, wherein the control timing signal for said first circuit means and the control timing signal for said second circuit means have their respective outputs controlled by said additional control signal.

Claim 16

A single chip semiconductor memory device for processing high-speed image data according to claim 12, wherein said memory unit includes dynamic random access memories.

Claim 17

A single chip semiconductor memory device for processing high-speed image data according to claim 11, further comprising: signal latch circuit means disposed at one input side of said arithmetic means for latching data signals fed from said memory unit; and data input circuit means disposed at another input side of said arithmetic means and having its operations controlled by the mask signals fed from said second circuits.

Claim 18

A single chip semiconductor memory device for processing high-speed image data according to claim 15, wherein said said input terminals are coupled to input nodes of data input circuit means, and said first and second circuit means are coupled to said input terminals.