US4932041A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for obtaining a bit-rate clock signal from a serial digital data signal
Assignee: Philips GmbH
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Filing: 1988-07-06
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Granted: 1990-06-05
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Expires: 2008-07-06
Abstract
Abstract To the phase locked loop for controlling the oscillator that regenerates a bit-rate clock signal from a data signal by means of a phase comparison circuit followed by a low pass filter, the output of which controls the oscillator frequency, a digital frequency comparison circuit is provided for assuring that the oscillator frequency will be brought into the capture range of the phase locked loop. The output of the digital frequency comparison circuit is converted from digital to analog form for being used in combination with the low pass filter output to control the oscillator. Frequency and phase control signals are applied to opposite electrodes of a variable capacitance diode in the frequency determining circuit of the oscillator. In order to improve the operation the frequency comparison circuit, delayed and undelayed oscillator output clock signals are sampled by transitions of the data signal for respectively incrementing or decrementing a counter, the state of which is then converted into an anlog signal for contributing to the control of the oscillator. The data signal also is provided in delayed and undelayed forms, and these are combined in an exclusive-OR gate, the output of which is used both in the phase comparison circuit and in the sampling portion the frequency comparison circuit. That portion of the frequency comparison circuit controls a pair of monoflops through D-flipflops so as to provide the necessary incrementing or decrementing pulses for the counter.
Inventors
- 👤 Berthold Eiberger
- 👤 Michael Philipps
- 👤 Rolf Schiffmann
- 👤 Peter Ries
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:35
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/113; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
339 words
Circuit for obtaining a bit-rate clock signal from a digital data signal, including a phase locked loop circuit comprising a phase comparison circuit, a low-pass filter and a controllable oscillator, said digital data signal and the output of said oscillator being supplied to said phase comparison circuit respectively at a data input and at a clock signal input thereof and the output of said phase comparison circuit providing an analog output voltage and being connected through said low pass filter to a control circuit of said oscillator, said low pass filter having an output connection, the output of said oscillator providing the bit-rate clock signal generated by the circuit, said circuit further comprising: a digital frequency comparison circuit (3) comprising means (36) for deriving a delayed clock signal from the clock signal output of said oscillator such that logic level transitions of said delayed clock signal are interleaved in time between logic level transitions of the undelayed clock signal, means for sampling said clock signal and said delayed clock signal at the occurrence of rising and falling flanks of said data signal, a bidirectional counter (39) having a count state output and connected so as to be incremented and decremented by outputs of said sampling means in a manner bringing the count state of said counter into correspondence with a reference value related to the bit frequency of said data signal; a digital to analog converter (9, 40) having an output and having its digital input connected to the count state output of said counter, and means (7) for applying the analog output of said digital to analog converter and the output of said low pass filter additively to a control circuit of said oscillator, whereby said output of said D/A converter is not filtered by said low pass filter, said clock signal output of said oscillator being directly connected to said delayed clock signal deriving means, to said sampling means of said digital frequency comparison circuit and also to said clock signal input of said phase comparison circuit.
Claim 2
Dependent Claim
339 words
Circuit for obtaining a bit-rate clock signal from a digital data signal, including a phase locked loop circuit comprising a phase comparison circuit, a low-pass filter and a controllable oscillator, said digital data signal and the output of said oscillator being supplied to said phase comparison circuit respectively at a data input and at a clock signal input thereof and the output of said phase comparison circuit providing an analog output voltage and being connected through said low pass filter to a control circuit of said oscillator, said low pass filter having an output connection, the output of said oscillator providing the bit-rate clock signal generated by the circuit, said circuit further comprising: a digital frequency comparison circuit (3) comprising means (36) for deriving a delayed clock signal from the clock signal output of said oscillator such that logic level transitions of said delayed clock signal are interleaved in time between logic level transitions of the undelayed clock signal, means for sampling said clock signal and said delayed clock signal at the occurrence of rising and falling flanks of said data signal, a bidirectional counter (39) having a count state output and connected so as to be incremented and decremented by outputs of said sampling means in a manner bringing the count state of said counter into correspondence with a reference value related to the bit frequency of said data signal; a digital to analog converter (9, 40) having an output and having its digital input connected to the count state output of said counter, and means (7) for applying the analog output of said digital to analog converter and the output of said low pass filter additively to a control circuit of said oscillator, whereby said output of said D/A converter is not filtered by said low pass filter, said clock signal output of said oscillator being directly connected to said delayed clock signal deriving means, to said sampling means of said digital frequency comparison circuit and also to said clock signal input of said phase comparison circuit.
Claim 3
Dependent Claim
60 words
Circuit according to claim 1 further comprising means (11) for delaying said data signal by half of a nominal bit period thereof and exclusive-OR circuit means (12) for combining the resulting delayed signal with said data signal as undelayed, the output of said exclusive-OR circuit means being connected to supply said combined data signal to said phase comparison means (13).
Claim 4
Dependent Claim
130 words
Circuit according to claim 2, wherein said means for sampling said delayed and undelayed clock signals together with said connection of said counter for incrementation and decrementation comprises: first and second D-flipflops (33, 34) having their clock inputs both connected to the output of said exclusive-OR gate circuit means (13) and having their data inputs respectively connected for receiving said clock signal and said delayed clock signal; third and fourth D-flipflops (37, 28) having their respective data inputs connected to an output of said first D-flipflop (33), the noninverting output of said second D-flipflop (34) being connected with the clock input of said fourth D-flipflop (38), said third and fourth flipflops being connected as monoflops and having outputs respectively connected to downcounting and upcounting inputs of said bidirectional counter (39).
Claim 5
Dependent Claim
64 words
Circuit according to claim 1, wherein said controllable oscillator comprises a frequency determining circuit including a variable capacitance diode (19) having one electrode thereof connected to the output of said digital to analog converter (9, 40) and another electrode to said low pass filter (6,14), whereby additive control of said oscillator by said phase comparison circuit and by said frequency comparison circuit is provided.
Claim 6
Dependent Claim
65 words
Circuit according to claim 2, wherein said controllable oscillator comprises a frequency determining circuit including a variable capacitance diode (19) having one electrode thereof connected to the output of said digital to analog converter (9, 40) and another electrode to said low pass filter (6, 14), whereby additive control of said oscillator by said phase comparison circuit and by said frequency comparison circuit is provided.
Claim 7
Dependent Claim
65 words
Circuit according to claim 3, wherein said controllable oscillator comprises a frequency determining circuit including a variable capacitance diode (19) having one electrode thereof connected to the output of said digital to analog converter (9, 40) and another electrode to said low pass filter (6, 14), whereby additive control of said oscillator by said phase comparison circuit and by said frequency comparison circuit is provided.
Claim 8
Dependent Claim
38 words
Circuit as defined in claim 4 comprising means for temporarily substituting, in place of the output of said digital to analog converter, a substantially constant voltage of predetermined value which is temporarily substituted for calibration or test purposes.
Claim 9
Dependent Claim
38 words
Circuit as defined in claim 5 comprising means for temporarily substituting, in place of the output of said digital to analog converter, a substantially constant voltage of predetermined value which is temporarily substituted for calibration or test purposes.
Claim 10
Dependent Claim
38 words
Circuit as defined in claim 6 comprising means for temporarily substituting, in place of the output of said digital to analog converter, a substantially constant voltage of predetermined value which is temporarily substituted for calibration or test purposes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-04 | 1993-12-04 | 1994-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-04 | 1997-12-04 | 1998-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-04 | 2001-12-04 | 2002-06-05 | $7700.00 | Window Closed / Lapsed |