Semiconductor memory device

Claim 2

A semiconductor memory device for storing data and selecting data to be read by a sensing amplifier, comprising: a plurality of memory cells for storing the data and arranged in a matrix, each memory cell including a MOS transistor having a source electrode and drain electrode; word lines arranged in rows; a plurality of first bit lines arranged in columns, each first bit line coupled to one of the source electrodes and drain electrodes of a plurality of MOS transistors wherein each column formed by said first bit lines includes at least two first bit lines and wherein the word lines and first bit lines are together operable for selecting one of the memory cells whereby the data stored in the selected memory cell serves as the selected data to be read by the sensing amplifier; at least one second bit line, each at least one second bit line selectively coupled to said at least two first bit lines within the same column; a power source line coupled to the other of the source electrodes and drain electrodes of a plurality of the MOS transitors; and bit line select means for selectively coupling each second bit line to the sensing amplifier.

Claim 3

The semiconductor memory device of claim 1 wherein the word lines act as gate electrodes for the MOS transistors forming the memory cells.

Claim 4

The semiconductor memory device of claim 1 wherein the first bit lines are formed of polycrystalline silicon.

Claim 5

The semiconductor memory device of claim 3 wherein the first bit lines are connected to one of the source and drain electrodes of a plurality of MOS transistors forming the memory cells by buried contacts.

Claim 6

The semiconductor memory device of claim 4 wherein the second bit line is formed of metal.

Claim 7

The semiconductor memory device of claim 4 wherein the first and second bit lines are formed as separate layers separated by an insulating layer, and further including additional bit line select means for selectively coupling the first and second bit lines together.

Claim 8

The semiconductor memory device of claim 3 further including a substrate having a plurality of diffusion areas which serve as the source and drain electrodes and a plurality of contact holes through which the plurality of first bit lines are coupled to the MOS transistors.

Claim 9

The semiconductor memory device of claim 1 wherein the first bit lines are formed of metal.

Claim 10

The semiconductor memory device of claim 8 further including a substrate having a plurality of diffusion areas which serve as the source and drain electrodes and a plurality of contact holes through which the plurality of first bit lines are coupled to the MOS transistors.

Claim 11

The semiconductor memory device of claim 1 wherein the second bit line is formed of metal.

Claim 12

The semiconductor memory device of claim 10 wherein the metal is aluminum.

Claim 13

The semiconductor memory device of claim 1 wherein the first and second bit lines are formed as separate layers separated by an insulating layer, and further including additional bit line select means for selectively coupling the first and second bit lines together.

Claim 14

The semiconductor memory device of claim 1 wherein the power source line includes a plurality of first source lines coupled to the other of the source and drain electrodes of a plurality of MOS transistors and at least one second source line coupled to at least one first source line at a contact.

Claim 15

The semiconductor memory device of claim 13 wherein the first source lines are formed of polycrystalline silicon.

Claim 16

The semiconductor memory device of claim 14 wherein the at least one second source line is formed of metal.

Claim 17

The semiconductor memory device of claim 13 wherein the at least one second source line is formed of metal.

Claim 18

The semiconductor memory device of claim 13 wherein the first source lines and the at least one second source line are formed as two layers separated by an insulating layer, except at the contact.

Claim 19

A semiconductor memory device for storing data and reading selected data, comprising: a plurality of memory cells for storing the data and arranged in a matrix, each memory cell including a MOS transistor having a source diffusion area and a drain diffusion area; word lines arranged in rows; a plurality of first bit lines arranged in columns, each first bit line electrically coupled to one of the source diffusion areas and drain diffusion areas of a plurality of MOS transistors wherein each column formed from said first bit lines includes at least two first bit lines and wherein the word lines and first bit lines are together operable for selecting one of the memory cells whereby data stored in the selected memory cell serves as the selected data to be read from the device; a second bit line selectively electrically coupled to at least two first bit lines; first bit line select means for selecting which one of the at least two first bit lines is to be electrically coupled to the second bit line; a plurality of first power source lines electrically coupled to the other of the source and drain diffusion areas of a plurality of MOS transistors; and a second power source line electrically coupled to the first power source lines.

Claim 20

A semiconductor memory device for storing data and reading selected data, comprising: a plurality of memory cells for storing the data and arranged in a matrix, each memory cell including a MOS transistor having a source diffusion area and a drain diffusion area; word lines arranged in rows; a plurality of first bit lines arranged in columns, each first bit line electrically coupled to one of the source diffusion areas and drain diffusion areas of a plurality of MOS transistors wherein each column formed from said first bit lines includes at least two first bit lines and wherein the word lines and first bit lines are together operable for selecting one of the memory cells whereby data stored in the selected memory cell serves as the selected data to be read from the device; a second bit line selectively electrically coupled to at least two first bit lines; first bit line select means for selecting which one of the at least two first bit lines is to be electrically coupled to the second bit line; a plurality of first power source lines electrically coupled to the other of the source and drain diffusion areas of a plurality of MOS transistors; and a second power source line electrically coupled to the first power source lines.

Claim 21

The semiconductor memory device of claim 18 wherein the first bit lines and the first power source line are arranged on a first layer.

Claim 22

The semiconductor memory device of claim 19 wherein the second bit line and the second power source line are arranged on a second layer, the second layer being generally separated from the first layer by an insulating layer.

Claim 23

The semiconductor memory device of claim 19 wherein the first bit line and the first power source line are formed of polycrystalline silicon.

Claim 24

The semiconductor memory device of claim 19 further including a plurality of contact holes through which the plurality of first bit lines are coupled to the MOS transistors.

Claim 25

The semiconductor memory device of claim 18 wherein the second bit line and the second power source line are arranged on a single layer.

Claim 26

The semiconductor memory device of claim 23 wherein the second bit line and the second power source line are formed of metal.

Claim 27

The semiconductor memory device of claim 18 wherein the first power source line is coupled to the other of the source and drain diffusion areas of a plurality of MOS transistors by buried contacts.

Claim 28

The semiconductor memory device of claim 18 wherein the first bit lines and the first power source lines are formed of polycrystalline silicon.

Claim 29

The semiconductor memory device of claim 26 wherein the plurality of first bit lines are connected to the source or drain diffusion areas of a plurality of MOS transistors by buried contacts.

Claim 30

The semiconductor memory device of claim 26 further including a plurality of contact holes through which the plurality of first bit lines are coupled to the MOS transistors.

Claim 31

The semiconductor memory device of claim 18 wherein the second bit line and the second power source line are formed of metal.

Claim 32

The semiconductor memory device of claim 29 wherein the first bit line is connected to the source or drain diffusion areas of a plurality of MOS transistors by buried contacts.

Claim 33

The semiconductor memory device of claim 18 wherein the plurality of first bit lines are connected to one of the source and drain diffusion areas of the MOS transistors by buried contacts.

Claim 34

The semiconductor memory device of claim 18 further comprising a sensing amplifier for detecting the data stored in selected memory cells, the sensing amplifier being selectively coupled to the second bit line.

Claim 35

The semiconductor memory device of claim 32 further including means for providing a reference current and wherein the sensing amplifier senses the data in a selected memory cell by comparison between current flowing on the second bit line and the reference current.

Claim 36

The semiconductor memory device of claim 18 wherein the MOS transistors further include gate electrodes and wherein the word lines are coupled to the gate electrodes of the MOS transistors.

Claim 37

The semiconductor memory device of claim 18 further including a plurality of contact holes through which the plurality of first bit lines are coupled to the MOS transistors.

Claim 38

A semiconductor memory device for storing data and reading selected data in combination with means for providing bit line select signals, comprising: a plurality of memory cells for storing the data and arranged in a matrix, each memory cell including a MOS transistor having source and drain electrodes wherein the matrix includes at least one column having at least two groups, each group including at least two memory cells; word lines arranged in rows; a plurality of first bit lines arranged in columns, each first bit line coupled to one of the source electrodes and drain electrodes of a plurality of MOS transistors wherein the word lines and first bit lines are together operable for selecting one of the memory cells; first bit line selection means including selection MOS transistors, each selection MOS transistor having source, drain and gate electrodes, each of the first bit lines coupled to one of the source and drain electrodes of one of the selection MOS transistors, the gate electrodes of the selection MOS transistors operable for receiving the bit line select signals and the other of the source and drain electrodes of the selection MOS transistors coupled to a common connection; a second bit line coupled to the common connection; and sensing means coupled to the second bit line for sensing the selected memory cell whereby data stored in the selected memory cell serves as the selected data to be read.

Claim 39

A semiconductor memory device for storing data and reading selected data in combination with means for providing bit line select signals, comprising: a plurality of memory cells for storing the data and arranged in a matrix, each memory cell including a MOS transistor having source and drain electrodes wherein the matrix includes at least one column having at least two groups, each group including at least two memory cells; word lines arranged in rows; a plurality of first bit lines arranged in columns, each first bit line coupled to one of the source electrodes and drain electrodes of a plurality of MOS transistors wherein the word lines and first bit lines are together operable for selecting one of the memory cells; first bit line selection means including selection MOS transistors, each selection MOS transistor having source, drain and gate electrodes, each of the first bit lines coupled to one of the source and drain electrodes of one of the selection MOS transistors, the gate electrodes of the selection MOS transistors operable for receiving the bit line select signals and the other of the source and drain electrodes of the selection MOS transistors coupled to a common connection; a second bit line coupled to the common connection; and sensing means coupled to the second bit line for sensing the selected memory cell whereby data stored in the selected memory cell serves as the selected data to be read.

Claim 40

The semiconductor memory device of claim 36 wherein the first bit lines are connected to the one of the source and drain electrodes of a plurality of MOS transistors forming the memory cells by buried contacts.

Claim 41

The semiconductor memory device of claim 36 wherein the sensing means comprises a sensing amplifier.

Claim 42

The semiconductor memory device of claim 38 further including means for providing a reference current and wherein the sensing amplifier reads the data stored in a memory cell by comparing the current flow through the MOS transistor forming the selected memory cell with the level of the reference current.

Claim 43

The semiconductor memory device of claim 36 wherein the first bit lines are formed of polycrystalline silicon.

Claim 44

The semiconductor memory device of claim 36 wherein the second bit line is formed of metal.

Claim 45

The semiconductor memory device of claim 36 further comprising a first power source line coupled to the other of the source and drain electrodes of a plurality of MOS transistors.

Claim 46

The semiconductor memory device of claim 42 further comprising a second power source line coupled to the first power source line.

Claim 47

The semiconductor memory device of claim 43 wherein the first power source line is formed of polycrystalline silicon and the second power source line is formed of metal.

Claim 48

The semiconductor memory device of claim 36 further including a substrate having a plurality of diffusion areas which serve as the source and drain electrodes of the MOS transistors and a plurality of contact holes through which the plurality of first bit lines are coupled to the MOS transistors.