US4924314A
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Semiconductor device containing video signal processing circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1987-09-09
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Granted: 1990-05-08
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Expires: 2007-09-09
Abstract
Abstract An integrated circuit 1 for video signal processing includes a 2-line memory 3, a video signal processing circuit 4 and a coincidence circuit 6. A digital video signal of 8 bits inputted to an input terminal group 2 is applied to the 2-line memory 3 and the coincidence circuit 6. Also, the 2-line delay signal of 8 bits outputted from the 2-line memory 3 is applied to the coincidence circuit 6. The coincidence circuit 6 determines coincidence or non-coincidence of the input digital video signal and the 2-line delay signal received and outputs the result of that determination through a coincidence output terminal. As a result, an operation of the 2-line memory 3 can be tested individually.
Inventors
- 👤 Masahiko Yoshimoto
- 👤 Hiroshi Segawa
- 👤 Tetsuya Matsumura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:54
CPC Classifications
H; H04; H04N; H04N17/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
223 words
A semiconductor device for processing video signals comprising: means (2) for providing a digital video signal of n bits (n is a positive integer); digital delay means (3) responsive to said digital video signal of n bits provided from said digital video signal providing means for outputting a 1-line through m-line (m is a positive integer) delay signal of said digital video signal of n bits; video signal processing means (4) responsive to said digital delay means output for performing video signal processing; and means for testing an operation of said digital delay means (3), including coincidence determining means (6) for (a) comparing said digital video signal of n bits inputted from said digital video signal providing means to said digital delay means and an l-line (l is an integer, 1 ≦l ≦ m) delay signal to be tested, out of said 1-line through m-line delay signal outputted from said digital delay means, and (b) determining coincidence of said digital video signal of n bits and said l-line delay signal, wherein said coincidence determining means comprises n exclusive OR circuit means (20-27) each performing an exclusive OR operation of the corresponding bits of said digital video signal of n bits and said line delay signal and OR means (28) for performing an OR operation of the outputs of said n exclusive OR means.
Claim 2
Dependent Claim
223 words
A semiconductor device for processing video signals comprising: means (2) for providing a digital video signal of n bits (n is a positive integer); digital delay means (3) responsive to said digital video signal of n bits provided from said digital video signal providing means for outputting a 1-line through m-line (m is a positive integer) delay signal of said digital video signal of n bits; video signal processing means (4) responsive to said digital delay means output for performing video signal processing; and means for testing an operation of said digital delay means (3), including coincidence determining means (6) for (a) comparing said digital video signal of n bits inputted from said digital video signal providing means to said digital delay means and an l-line (l is an integer, 1 ≦l ≦ m) delay signal to be tested, out of said 1-line through m-line delay signal outputted from said digital delay means, and (b) determining coincidence of said digital video signal of n bits and said l-line delay signal, wherein said coincidence determining means comprises n exclusive OR circuit means (20-27) each performing an exclusive OR operation of the corresponding bits of said digital video signal of n bits and said line delay signal and OR means (28) for performing an OR operation of the outputs of said n exclusive OR means.
Claim 3
Dependent Claim
238 words
A semiconductor device for processing video signals comprising: means (2) for providing a digital video signal of n bits (n is a positive integer) including analog-digital converting means (13) for converting an externally applied analog video signal into said digital video signal of n bits; digital delay means (3) responsive to said digital video signal of n bits provided from said digital video signal providing means for outputting a 1-line through m-line (m is a positive integer) delay signal of said digital video signal of n bits; video signal processing means (4) responsive to said digital delay means output for performing video signal processing; and means for testing an operation of said digital delay means (3), including coincidence determining means (6) for (a) comparing said digital video signal of n bits inputted from said digital video signal providing means to said digital delay means and an l-line (l is an integer, 1 ≦l ≦ m) delay signal to be tested, out of said 1-line through m-line delay signal outputted from said digital delay means, and (b) determining coincidence of said digital video signal of n bits and said l-line delay signal, wherein said analog-digital converting means comprises switching means (31) for replacing specific less significant bits out of said converted digital video signal of n bits with specific more significant bits out of said converted video signal of n bits at a test of said digital delay means.
Claim 4
Dependent Claim
238 words
A semiconductor device for processing video signals comprising: means (2) for providing a digital video signal of n bits (n is a positive integer) including analog-digital converting means (13) for converting an externally applied analog video signal into said digital video signal of n bits; digital delay means (3) responsive to said digital video signal of n bits provided from said digital video signal providing means for outputting a 1-line through m-line (m is a positive integer) delay signal of said digital video signal of n bits; video signal processing means (4) responsive to said digital delay means output for performing video signal processing; and means for testing an operation of said digital delay means (3), including coincidence determining means (6) for (a) comparing said digital video signal of n bits inputted from said digital video signal providing means to said digital delay means and an l-line (l is an integer, 1 ≦l ≦ m) delay signal to be tested, out of said 1-line through m-line delay signal outputted from said digital delay means, and (b) determining coincidence of said digital video signal of n bits and said l-line delay signal, wherein said analog-digital converting means comprises switching means (31) for replacing specific less significant bits out of said converted digital video signal of n bits with specific more significant bits out of said converted video signal of n bits at a test of said digital delay means.
Claim 5
Dependent Claim
25 words
A semiconductor device in accordance with claim 2, wherein said switching means comprises logically inverting means (32-35) for inverting said specific more significant bits 14.
Claim 6
Dependent Claim
26 words
A semiconductor device in accordance with claim 2, wherein said specific bits comprises more significant n/2 bits and said specific less significant bits comprises n/2 bits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-07 | 1993-11-06 | 1994-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-07 | 1997-11-06 | 1998-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-07 | 2001-11-06 | 2002-05-08 | $7700.00 | Window Closed / Lapsed |