US4924307A
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US
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Image processor
Assignee: Allen Bradley Co LLC
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Filing: 1988-06-03
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Granted: 1990-05-08
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Expires: 2008-06-03
Abstract
Abstract An image processor is divided into three sections for image acquisition and storage, image processing, and video output signal generation. The three sections are connected by an addrsss bus, a data bus and a set of control signal lines. A first bus control circuit is provided to isolate the image acquisition and storage section from the other sections during image acquisition and storage operations. A second bus control circuit isolates the video output section from the other sections, except during vertical and horizontal blanking intervals of the video output signal. The image is acquired by a line scan sensor which is clocked to acquire the image over one of several user definable exposure intervals. The video output presents the line scan sensor image in three formats. The first is a compressed representation of the entire line and the second is a less compressed representation of a selected portion of the image. The third display format is a binary version of the second image display format.
Inventors
- 👤 Roger W. Landowski
- 👤 Richard M. Roszkowski
- 👤 Donald J. Christian
- 👤 Assad A. Ansari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:18
CPC Classifications
G; G06; G06T; G06T1/00; G06T1/20
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
262 words
An image processor comprising: a data bus divided into first and second sections; an address bus divided into first, second and third sections; an analog to digital converter, coupled to the second section of said data bus, for receiving an analog signal representing an image to be processed and for producing digitized representations of image elements of the image; a first memory means coupled to the second section of said data bus for storing the digitized representations of the image elements; a first means, coupled to the second section of said address bus, for addressing said first memory means; means for generating a first coupling signal whenever the first means for addressing is not addressing said first memory means; a first means, responsive to the first coupling signal, for coupling the first and second sections of said data bus together and for coupling the first and second sections of said address bus together; means, coupled to the first sections of said address and data buses, for processing the digitized representations of the image elements; a second memory means coupled to the third section of said address bus and to the second section of said data bus for storing video image data; a second means, coupled to the third section of said address bus, for addressing said second memory means; means for generating a second coupling signal whenever the second means for addressing is not addressing said second memory means; and a second means for coupling the first and third sections of said address bus together in response to a second coupling signal.
Claim 2
Dependent Claim
262 words
An image processor comprising: a data bus divided into first and second sections; an address bus divided into first, second and third sections; an analog to digital converter, coupled to the second section of said data bus, for receiving an analog signal representing an image to be processed and for producing digitized representations of image elements of the image; a first memory means coupled to the second section of said data bus for storing the digitized representations of the image elements; a first means, coupled to the second section of said address bus, for addressing said first memory means; means for generating a first coupling signal whenever the first means for addressing is not addressing said first memory means; a first means, responsive to the first coupling signal, for coupling the first and second sections of said data bus together and for coupling the first and second sections of said address bus together; means, coupled to the first sections of said address and data buses, for processing the digitized representations of the image elements; a second memory means coupled to the third section of said address bus and to the second section of said data bus for storing video image data; a second means, coupled to the third section of said address bus, for addressing said second memory means; means for generating a second coupling signal whenever the second means for addressing is not addressing said second memory means; and a second means for coupling the first and third sections of said address bus together in response to a second coupling signal.
Claim 3
Dependent Claim
51 words
The image processor as recited in claim 1 further comprising an image sensor which produces an analog signal that is coupled to said analog to digital converter, and having a plurality of image element sites for holding a charge proportional to the amount of light impinging upon the sensor over time.
Claim 4
Dependent Claim
31 words
The image processor as recited in claim 2 further comprising means for selectively defining the amount of time that the charge accumulates in the image element sites of said image sensor.
Claim 5
Dependent Claim
35 words
The image processor as recited in claim 1 wherein said means for processing the digitized representations of the image elements comprises a memory and a microprocessor for respectively storing and executing an image analysis program.
Claim 6
Dependent Claim
34 words
The image processor as recited in claim 4 wherein said image analysis program includes means for numerically processing the image elements; and for performing an arithmetic operation on the results of the numerical processing.
Claim 7
Dependent Claim
35 words
The image processor as recited in claim 1 further comprising means for generating an analog signal having a magnitude which varies in response to said means for processing the digitized representations of the image elements.
Claim 8
Dependent Claim
31 words
The image processor as recited in claim 1 further comprising means for generating a digital output signal in response to said means for processing the digitized representations of the image elements.
Claim 9
Dependent Claim
36 words
The image processor as recited in claim 1 further comprising means for periodically enabling said first memory means to store image elements of an image, such enabling being at a selectable interval from the previous enabling.
Claim 10
Dependent Claim
81 words
An image processor comprising: a light sensor means for producing a signal representing a series of image elements in a linear image; means for storing the luminance level of each of the series of image elements from said sensor means; means for processing the luminance levels of the series of image elements to produce a video image having a first format displaying a compressed representation of the full linear image, a second format displaying a selected portion of the linear image.
Claim 11
Dependent Claim
81 words
An image processor comprising: a light sensor means for producing a signal representing a series of image elements in a linear image; means for storing the luminance level of each of the series of image elements from said sensor means; means for processing the luminance levels of the series of image elements to produce a video image having a first format displaying a compressed representation of the full linear image, a second format displaying a selected portion of the linear image.
Claim 12
Dependent Claim
26 words
The image processor as recited in claim 9 wherein the first and second image formats display a representation of the luminance levels of selected image elements.
Claim 13
Dependent Claim
71 words
The image processor as recited in claim 10 wherein each of the first and second image formats is a two dimensional graph with the selected image elements being represented at a position on the graph having a coordinate along a first axis which corresponds to the position of the image element in the linear image, and a coordinate along a second axis corresponds to the luminance level of that image element.
Claim 14
Dependent Claim
30 words
The image processor as recited in claim 10 wherein the video image further comprises a third format displaying a binary representation of the selected image elements of the second format.
Claim 15
Dependent Claim
129 words
An image processor comprising: an analog to digital converter for receiving an analog signal representing an image to be processed and for generating digitized representations of image elements of the image; an first memory coupled to said analog to digital converter for storing the digitized representations of the image elements of the image; means for addressing said first memory; means for analyzing the digitized representations of the image elements to produce at least one analysis result; a video output circuit having a second memory for storing video image data representing the image elements, means for addressing said second memory, and means for generating a video signal from the video image data; and a first output means for producing an analog signal having a magnitude which represents one analysis result.
Claim 16
Dependent Claim
129 words
An image processor comprising: an analog to digital converter for receiving an analog signal representing an image to be processed and for generating digitized representations of image elements of the image; an first memory coupled to said analog to digital converter for storing the digitized representations of the image elements of the image; means for addressing said first memory; means for analyzing the digitized representations of the image elements to produce at least one analysis result; a video output circuit having a second memory for storing video image data representing the image elements, means for addressing said second memory, and means for generating a video signal from the video image data; and a first output means for producing an analog signal having a magnitude which represents one analysis result.
Claim 17
Dependent Claim
27 words
The image processor as recited in claim 13 further comprising a second output means for producing a digital signal having a magnitude which represents another analysis result.
Claim 18
Dependent Claim
24 words
The image processor as recited in claim 13 further comprising a linear image sensor coupled to an input of said analog to digital converter.
Claim 19
Dependent Claim
32 words
The image processor as recited in claim 13 further comprising means for periodically enabling said first memory to store the digitized representations of the image elements, such enabling occurring at selectable intervals.
Claim 20
Dependent Claim
49 words
The image processor as recited in claim 13 further comprising means for enabling said first memory to store the digitized representations of the image elements and having a timer means, such enabling being in response to either an externally produced signal or to a signal from the timer means.
Claim 21
Dependent Claim
69 words
The image processor as recited in claim 13 further comprising: a charge coupled device image sensor which accumulates charge in each of a plurality of image element sites in response to the amount of light striking each site, said image sensor being coupled to said analog to digital converter; and means for varying the time interval during which charge accumulates in the image elements sites of said image sensor.
Claim 22
Dependent Claim
30 words
The image processor as recited in claim 13 wherein said means for analyzing produces a two numerical results and includes means for performing an arithmetic operation on the numerical results.
Claim 23
Dependent Claim
40 words
The image processor as recited in claim 13 wherein said means for analyzing includes means for limiting the analysis to sections of the image having at least a predetermined number of contiguous image elements which have a predefined common characteristic.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-07 | 1993-11-06 | 1994-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-07 | 1997-11-06 | 1998-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-07 | 2001-11-06 | 2002-05-08 | $7700.00 | Window Closed / Lapsed |